design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

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design a pipelined CPU  using Verilog HDL. i have all the components (.v files) created. Just need help connecting them with a testbench and knowing how to demonstrate the sum instruction

 

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  • 13 years ago
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perfecto
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    pipeline.rar
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Nerd
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    pipeline.rar
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    assembly.txt
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    answers_to_the_3_questions.docx
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    truthtable.xls
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