design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:34:17 06/01/2013 // Design Name: // Module Name: Pipeline // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Pipeline( input clock, input reset, output [31:0] instruction ); wire [31:0] inPC; wire [31:0] outPC; wire [31:0] AddedPC; // PC + 4 Result wire [31:0] InstFromMem; wire [31:0] RegData1; wire [31:0] RegData2; wire [31:0] MemFromData; wire [31:0] MemOrReg; // Result from mux wire [31:0] PCorReg; // Result from mux wire [31:0] ALUOut; // Result from ALU wire [3:0] ALUSrc; // Control wire [0:0] MW; // Control wire [0:0] MR; // Control wire [0:0] J; // Control wire [0:0] JM; // Control wire [0:0] BZ; // Control wire [0:0] BN; // Control wire [0:0] LPC; // Control wire [0:0] RW; // Control wire [0:0] Z; // ALU Result - Zero wire [0:0] N; // ALU Result - Negative PC A1 (.in(inPC), .clock(clock), .out(outPC)); InstMem A2 (.PC(outPC), .clock(clock), .inst(InstFromMem)); Control A3 (.OpCode(InstFromMem[31:28]), .ALUControl(ALUSrc), .MemWrite(MW), .MemRead(MR), .Jump(J), .JumpMem(JM), .BifZ(BZ), .BifN(BN), .LoadPC(LPC), .RegWrite(RW)); RegMem A4 (.RdReg1(InstFromMem[21:16]), .RdReg2(InstFromMem[15:10]), .DestReg(InstFromMem[27:22]), .clock(clock), .RegWrite(RW), .RdData1(RegData1), .RdData2(RegData2), .WriteData(MemOrReg)); TwoToOneMux A5 (.Selector(LPC), .A(RegData1), .B(outPC), .Out(PCorReg)); ALU A6 (.IN1(PCorReg), .IN2(RegData2), .ALUControl(ALUSrc), .OUT(ALUOut), .Negative(N), .Zero(Z)); DataMemory A7 (.address(PCorReg), .writedata(RegData2), .memwrite(MW), .memread(MR), .clock(clock), .readdata(MemFromData)); TwoToOneMux A8 (.Selector(MR), .A(ALUOut), .B(MemFromData), .Out(MemorReg)); Adder A9 (.A(outPC), .B(4), .Y(AddedPC)); JumpOrBranch A10 (.PC(outPC), .BifZ(BZ), .BifN(BN), .Neg(N), .Zero(Z), .J(J), .JM(JM), .RegValue(RegData1), .MemValue(MemFromData), .NewPC(inPC)); endmodule