design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:41:22 05/21/2013 // Design Name: // Module Name: ALU // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module ALU( input [31:0] IN1, input [31:0] IN2, input [3:0] ALUControl, output reg [31:0] OUT, output reg Zero, output reg Negative ); always @(IN1 or IN2 or ALUControl) begin // Add if(ALUControl == 8) OUT = IN1 + IN2; // Increment else if(ALUControl == 4) OUT = IN1 + 1; // Negative else if(ALUControl == 2) OUT = -IN1; // Subtract else if(ALUControl == 1) OUT = IN1 - IN2; // Pass A else OUT = IN1; end assign Zero = (OUT==0)? 1:0; assign Negative = (OUT<0) ? 1:0; endmodule