design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:32:16 05/21/2013 // Design Name: // Module Name: RegMem // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module RegMem( input [5:0] RdReg1, input [5:0] RdReg2, input [5:0] DestReg, input [31:0] WriteData, input clock, input RegWrite, output reg [31:0] RdData1, output reg [31:0] RdData2 ); reg[31:0] registers[2047:0]; initial begin $readmemb("registers.txt", registers); end always @(posedge clock) begin RdData1 = registers[RdReg1]; RdData2 = registers[RdReg2]; end always @(negedge clock) begin if(RegWrite == 1) begin registers[DestReg] = WriteData; end end endmodule