design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:58:19 04/30/2013 // Design Name: // Module Name: InstFetch // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module InstFetch( input clock, input reset, output [31:0] instruction ); wire [31:0] X; wire [31:0] Y; PC A1 (.in(X), .clock(clock), .out(Y)); InstMem A2 (.PC(Y), .clock(clock), .inst(instruction)); Adder A3 (.A(Y), .B(4), .Y(X)); endmodule