design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 16:08:56 06/01/2013 // Design Name: // Module Name: Control // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Control( input [3:0] OpCode, output reg [3:0] ALUControl, // ALU output reg MemWrite, // Data Mem output reg MemRead, // Data Mem output reg Jump, // Jump Mux output reg JumpMem, // Jump Mem Mux output reg BifZ, // Branch if Zero AND output reg BifN, // Branch if Neg AND output reg LoadPC, // RS/PC Mux output reg RegWrite // Reg ); always @(OpCode) begin // Long "if" statement to go through opcode if(OpCode == 0) begin // No operation ALUControl = 0; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end else if(OpCode == 15) begin // Load PC ALUControl = 15; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 1; RegWrite = 1; end else if(OpCode == 14) begin // Load ALUControl = 15; MemWrite = 0; MemRead = 1; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 3) begin // Store ALUControl = 15; MemWrite = 1; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end else if(OpCode == 4) begin // Add ALUControl = 8; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 5) begin // Increment ALUControl = 4; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 6) begin // Negate ALUControl = 2; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 7) begin // Subtract ALUControl = 1; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 8) begin // Jump ALUControl = 0; MemWrite = 0; MemRead = 0; Jump = 1; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end else if(OpCode == 9) begin // Branch if Zero ALUControl = 15; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 1; BifN = 0; LoadPC = 0; RegWrite = 0; end else if(OpCode == 10) begin // Jump Memory ALUControl = 15; MemWrite = 0; MemRead = 1; Jump = 0; JumpMem = 1; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end else if(OpCode == 11) begin // Branch if Negative ALUControl = 15; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 1; end else if(OpCode == 1) begin // Sum ALUControl = 0; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end else ALUControl = 0; MemWrite = 0; MemRead = 0; Jump = 0; JumpMem = 0; BifZ = 0; BifN = 0; LoadPC = 0; RegWrite = 0; end endmodule