design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:25:31 04/23/2013 // Design Name: // Module Name: DataMemory // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module DataMemory( input [31:0] address, input [31:0] writedata, input memwrite, input memread, input clock, output reg [31:0] readdata ); // address = reg 1 // writedata = reg 2 // readdata = destination reg reg[31:0] memory[255:0]; // to split between memread and memwrite, have memwrite on posedge and memread on negedge always @(posedge clock) begin // write memory, only if memwrite is 1 if(memwrite == 1) begin memory[address] = writedata; end end always @(negedge clock) begin // read memory, only if memread is 1 if(memread == 1) begin readdata = memory[address]; end end endmodule