design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

For the project demos, be prepared with your testbench and memory array values to implement the sum instruction. So prepare a testbench, load your instruction memory with the sum instruction, load your data memory with 4 values 2 3 5 and -7. Thus the value of N will be 4 in this case. Later when I ask you to demo with different values all you will need to do is make changes in your instruction and data memory.