design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:08:25 04/23/2013 // Design Name: // Module Name: PC // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module PC( input [31:0] in, input clock, output reg [31:0] out ); initial begin out = 0; end always @(posedge clock) begin // when clock edge is positive, set 'out' equal to 'in' out = in; end endmodule