design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:06:44 04/30/2013 // Design Name: // Module Name: InstMem // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module InstMem( input [31:0] PC, input clock, output reg [31:0] inst ); reg[31:0] mem[1023:0]; initial begin $readmemb("instruction.txt", mem); end always @(posedge clock) begin inst = mem[PC]; end endmodule