design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:21:36 06/01/2013 // Design Name: // Module Name: JumpOrBranch // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module JumpOrBranch( input [31:0] PC, input BifN, input Neg, input BifZ, input Zero, input J, input JM, input [31:0] RegValue, input [31:0] MemValue, output reg [31:0] NewPC ); always @(PC) begin if(J == 1) // Check if Jump NewPC = RegValue; else if(BifN & Neg) // Check if Negative and Branch NewPC = RegValue; else if(BifZ & Zero) // Check if Zero and Branch NewPC = RegValue; else if(JM == 1) // Check if Jump Memory NewPC = MemValue; else NewPC = PC; // Reg. PC + 4 end endmodule