design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 21:52:25 06/01/2013 // Design Name: // Module Name: TwoToOneMux // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module TwoToOneMux( input Selector, input [31:0] A, input [31:0] B, output reg [31:0] Out ); always @(A or B or Selector) begin // A if 0 if(Selector == 0) // B if 1 Out = A; else Out = B; end endmodule