design a structural model of a pipelined CPU with 13 instructions using Verilog HDL. i have all the components (.v...
diae_k
adder.v`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:43:20 04/08/2013 // Design Name: // Module Name: Adder // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Adder( input [31:0] A, input [31:0] B, output [31:0] Y ); assign Y = A + B; endmodule
