VHDL assignment,one week dead line,if u have any doubts,plz let me know,even though i am unware of those,will take help from tutor

3000-5000 words approximately ,word document,one week deadline,harward ref

Assignment.............plz do acc to the specifications,tasks,sub tasks,waveforms,zoom-in,eqi.circuit,comparision and all

divclk waveform .............i got in lab,just for ref i am sending u

all jpeg files.........my tutor has given some clue about the task1,go through it and made any changes if nessary

Div ERROR DIAGRAM.............:this is the structure to use,while creating the sv source description

ZIP:......................documents related to task 12

TASK 5 FSM:................it is also some clue,have to fill all 5 states

XADC_DISPLAY_RTL:.............not at all related to this assignment,sending u for ref..all wave forms,program should be this much clear