VHDL assignment,one week dead line,if u have any doubts,plz let me know,even though i am unware of those,will take help from tutor

Map ‘ErrRate’ to ‘Bits_between_errors’(according to table below)ErrRate[2:0]

ErrRate Bits between errors* Bit Error Rate (%)

0 99 1%

1 49 2%

2 19 5%

3 9 10%

4 4 20%

5 3 25%

6 2 33⅓%

7 1 50%

*BBECompare BBE with Counter outputBBE[6:0]Count[6:0]BBE_equals_CountError_Onerrorbit_enClock_enable#resetclockLoad**0000000** Synchronous parallel load from D.# enables synchronous clocking when high.D7-bit counterQ

Map ‘ErrRate’ to ‘Bits_between_errors’ (according to table below) ErrRate[2:0] *BBE Compare BBE with Counter output BBE[6:0] Count[6:0] BBE_equals_Count Error_On error bit_en Clock_enable# reset clock Load** 0000000 ** Synchronous parallel load from D. # enables synchronous clocking when high. D 7-bit counter Q