VHDL assignment,one week dead line,if u have any doubts,plz let me know,even though i am unware of those,will take help from tutor
chenponlineassighmenthelp
XADC_RTL_v2017.zipBasys3_XADC_RTL.xdc
## This file is a general .xdc for the Basys3 rev B board ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock signal set_property PACKAGE_PIN W5 [get_ports CLK100M] set_property IOSTANDARD LVCMOS33 [get_ports CLK100M] #create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK100M] ## Switches set_property PACKAGE_PIN V17 [get_ports sw[0]] set_property IOSTANDARD LVCMOS33 [get_ports sw[0]] set_property PACKAGE_PIN V16 [get_ports sw[1]] set_property IOSTANDARD LVCMOS33 [get_ports sw[1]] set_property PACKAGE_PIN W16 [get_ports sw[2]] set_property IOSTANDARD LVCMOS33 [get_ports sw[2]] set_property PACKAGE_PIN W17 [get_ports sw[3]] set_property IOSTANDARD LVCMOS33 [get_ports sw[3]] set_property PACKAGE_PIN W15 [get_ports sw[4]] set_property IOSTANDARD LVCMOS33 [get_ports sw[4]] set_property PACKAGE_PIN V15 [get_ports sw[5]] set_property IOSTANDARD LVCMOS33 [get_ports sw[5]] set_property PACKAGE_PIN W14 [get_ports sw[6]] set_property IOSTANDARD LVCMOS33 [get_ports sw[6]] set_property PACKAGE_PIN W13 [get_ports sw[7]] set_property IOSTANDARD LVCMOS33 [get_ports sw[7]] #set_property PACKAGE_PIN V2 [get_ports {sw[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] #set_property PACKAGE_PIN T3 [get_ports {sw[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] #set_property PACKAGE_PIN T2 [get_ports {sw[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] #set_property PACKAGE_PIN R3 [get_ports {sw[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] #set_property PACKAGE_PIN W2 [get_ports {sw[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] #set_property PACKAGE_PIN U1 [get_ports {sw[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] #set_property PACKAGE_PIN T1 [get_ports {sw[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] #set_property PACKAGE_PIN R2 [get_ports {sw[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] ## LEDs #set_property PACKAGE_PIN U16 [get_ports LED0] #set_property IOSTANDARD LVCMOS33 [get_ports LED0] #set_property PACKAGE_PIN E19 [get_ports LED1] #set_property IOSTANDARD LVCMOS33 [get_ports LED1] #set_property PACKAGE_PIN U19 [get_ports LED2] #set_property IOSTANDARD LVCMOS33 [get_ports LED2] #set_property PACKAGE_PIN V19 [get_ports LED3] #set_property IOSTANDARD LVCMOS33 [get_ports LED3] #set_property PACKAGE_PIN W18 [get_ports {led[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] #set_property PACKAGE_PIN U15 [get_ports {led[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] #set_property PACKAGE_PIN U14 [get_ports {led[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] #set_property PACKAGE_PIN V14 [get_ports {led[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] #set_property PACKAGE_PIN V13 [get_ports {led[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] #set_property PACKAGE_PIN V3 [get_ports {led[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] #set_property PACKAGE_PIN W3 [get_ports {led[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] #set_property PACKAGE_PIN U3 [get_ports {led[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] #set_property PACKAGE_PIN P3 [get_ports {led[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] #set_property PACKAGE_PIN N3 [get_ports {led[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] #set_property PACKAGE_PIN P1 [get_ports {led[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] #set_property PACKAGE_PIN L1 [get_ports {led[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##7 segment display set_property PACKAGE_PIN W7 [get_ports CA] set_property IOSTANDARD LVCMOS33 [get_ports CA] set_property PACKAGE_PIN W6 [get_ports CB] set_property IOSTANDARD LVCMOS33 [get_ports CB] set_property PACKAGE_PIN U8 [get_ports CC] set_property IOSTANDARD LVCMOS33 [get_ports CC] set_property PACKAGE_PIN V8 [get_ports CD] set_property IOSTANDARD LVCMOS33 [get_ports CD] set_property PACKAGE_PIN U5 [get_ports CE] set_property IOSTANDARD LVCMOS33 [get_ports CE] set_property PACKAGE_PIN V5 [get_ports CF] set_property IOSTANDARD LVCMOS33 [get_ports CF] set_property PACKAGE_PIN U7 [get_ports CG] set_property IOSTANDARD LVCMOS33 [get_ports CG] set_property PACKAGE_PIN V7 [get_ports DP] set_property IOSTANDARD LVCMOS33 [get_ports DP] set_property PACKAGE_PIN U2 [get_ports AN0] set_property IOSTANDARD LVCMOS33 [get_ports AN0] set_property PACKAGE_PIN U4 [get_ports AN1] set_property IOSTANDARD LVCMOS33 [get_ports AN1] set_property PACKAGE_PIN V4 [get_ports AN2] set_property IOSTANDARD LVCMOS33 [get_ports AN2] set_property PACKAGE_PIN W4 [get_ports AN3] set_property IOSTANDARD LVCMOS33 [get_ports AN3] ##Buttons set_property PACKAGE_PIN U18 [get_ports RESET] set_property IOSTANDARD LVCMOS33 [get_ports RESET] #set_property PACKAGE_PIN T18 [get_ports btnU] #set_property IOSTANDARD LVCMOS33 [get_ports btnU] #set_property PACKAGE_PIN W19 [get_ports btnL] #set_property IOSTANDARD LVCMOS33 [get_ports btnL] #set_property PACKAGE_PIN T17 [get_ports btnR] #set_property IOSTANDARD LVCMOS33 [get_ports btnR] set_property PACKAGE_PIN U17 [get_ports ManConv] set_property IOSTANDARD LVCMOS33 [get_ports ManConv] ##Pmod Header JA ##Sch name = JA1 set_property PACKAGE_PIN J1 [get_ports JA[0]] set_property IOSTANDARD LVCMOS33 [get_ports JA[0]] #Sch name = JA2 set_property PACKAGE_PIN L2 [get_ports JA[1]] set_property IOSTANDARD LVCMOS33 [get_ports JA[1]] #Sch name = JA3 set_property PACKAGE_PIN J2 [get_ports JA[2]] set_property IOSTANDARD LVCMOS33 [get_ports JA[2]] #Sch name = JA4 set_property PACKAGE_PIN G2 [get_ports JA[3]] set_property IOSTANDARD LVCMOS33 [get_ports JA[3]] #Sch name = JA7 set_property PACKAGE_PIN H1 [get_ports JA[4]] set_property IOSTANDARD LVCMOS33 [get_ports JA[4]] #Sch name = JA8 set_property PACKAGE_PIN K2 [get_ports JA[5]] set_property IOSTANDARD LVCMOS33 [get_ports JA[5]] #Sch name = JA9 set_property PACKAGE_PIN H2 [get_ports JA[6]] set_property IOSTANDARD LVCMOS33 [get_ports JA[6]] #Sch name = JA10 set_property PACKAGE_PIN G3 [get_ports JA[7]] set_property IOSTANDARD LVCMOS33 [get_ports JA[7]] ##Pmod Header JB ##Sch name = JB1 #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] ##Sch name = JB2 #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] ##Sch name = JB3 #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] ##Sch name = JB4 #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] ##Sch name = JB7 #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] ##Sch name = JB8 #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] ##Sch name = JB9 #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] ##Sch name = JB10 #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] ##Pmod Header JC ##Sch name = JC1 #set_property PACKAGE_PIN K17 [get_ports JC[0]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[0]] ##Sch name = JC2 #set_property PACKAGE_PIN M18 [get_ports JC[1]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[1]] ##Sch name = JC3 #set_property PACKAGE_PIN N17 [get_ports JC[2]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[2]] ##Sch name = JC4 #set_property PACKAGE_PIN P18 [get_ports JC[3]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[3]] ##Sch name = JC7 #set_property PACKAGE_PIN L17 [get_ports JC[4]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[4]] ##Sch name = JC8 #set_property PACKAGE_PIN M19 [get_ports JC[5]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[5]] ##Sch name = JC9 #set_property PACKAGE_PIN P17 [get_ports JC[6]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[6]] ##Sch name = JC10 #set_property PACKAGE_PIN R18 [get_ports JC[7]] # set_property IOSTANDARD LVCMOS33 [get_ports JC[7]] ##Pmod Header JXADC ##Sch name = XA1_P set_property PACKAGE_PIN J3 [get_ports VAUXP6] set_property IOSTANDARD LVCMOS33 [get_ports VAUXP6] ##Sch name = XA2_P #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Sch name = XA3_P #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Sch name = XA4_P #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Sch name = XA1_N set_property PACKAGE_PIN K3 [get_ports VAUXN6] set_property IOSTANDARD LVCMOS33 [get_ports VAUXN6] ##Sch name = XA2_N #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Sch name = XA3_N #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Sch name = XA4_N #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] ##VGA Connector #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] #set_property PACKAGE_PIN P19 [get_ports Hsync] #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] #set_property PACKAGE_PIN R19 [get_ports Vsync] #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] ##USB-RS232 Interface #set_property PACKAGE_PIN B18 [get_ports RsRx] #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] #set_property PACKAGE_PIN A18 [get_ports RsTx] #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] ##USB HID (PS/2) #set_property PACKAGE_PIN C17 [get_ports PS2Clk] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] #set_property PULLUP true [get_ports PS2Clk] #set_property PACKAGE_PIN B17 [get_ports PS2Data] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] #set_property PULLUP true [get_ports PS2Data] ##Quad SPI Flash ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the ##STARTUPE2 primitive. #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] #set_property PACKAGE_PIN K19 [get_ports QspiCSn] #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
bcd2seg.sv
module bcd2seg #(parameter Active_High = 0) (input logic [3:0] bcdin, output logic CA, CB, CC, CD, CE, CF, CG); logic [6:0] temp; always_comb case(bcdin) //active-low codes 4'h0 : temp = 7'b0000001; 4'h1 : temp = 7'b1001111; 4'h2 : temp = 7'b0010010; 4'h3 : temp = 7'b0000110; 4'h4 : temp = 7'b1001100; 4'h5 : temp = 7'b0100100; 4'h6 : temp = 7'b0100000; 4'h7 : temp = 7'b0001111; 4'h8 : temp = 7'b0000000; 4'h9 : temp = 7'b0000100; 4'hA : temp = 7'b0001000; 4'hB : temp = 7'b1100000; 4'hC : temp = 7'b0110001; 4'hD : temp = 7'b1000010; 4'hE : temp = 7'b0110000; 4'hF : temp = 7'b0111000; endcase assign {CA, CB, CC, CD, CE, CF, CG} = (Active_High)? ~temp : temp; endmodule : bcd2seg
design3.txt
TIME VAUXP[6] VAUXN[6] 0 0.0 0.0 3000 0.2 0.0 5000 0.4 0.0 7000 0.6 0.0 9000 0.8 0.0 11000 0.99 0.0
DispCntr.sv
//modified for BASYS3 Board with 100MHz input clock module dispcntr #(parameter N = 2) (input logic Clk, Reset, output logic AN0, AN1, AN2, AN3, //active-low anodes output logic [1:0] sel); //divides clock input by 2**N //used by multiplexed displays //set N = 2 for simulation and //N = 22 for implementation (100e6/2**20 = 95Hz) reg [N-1:0] count; always_ff @(posedge Clk or posedge Reset) begin if (Reset == 1'b1) count <= 0; else count <= count + 1; end assign sel = count[N-1:N-2]; //top 2 bits of count //active low common anodes assign AN0 = ~(sel == 0); assign AN1 = ~(sel == 1); assign AN2 = ~(sel == 2); assign AN3 = ~(sel == 3); endmodule : dispcntr
DispMux.sv
module dispmux (input logic [15:0] datain, output logic [3:0] bcd_out, input logic [1:0] sel); //16-to-4 mux for display always_comb case (sel) 0 : bcd_out = datain[3:0]; 1 : bcd_out = datain[7:4]; 2 : bcd_out = datain[11:8]; 3 : bcd_out = datain[15:12]; endcase endmodule : dispmux
testbench.sv
`timescale 1ns / 1ps module testbench(); logic RESET, CLK100M; logic VAUXP6, VAUXN6; logic CA, CB, CC, CD, CE, CF, CG, DP, AN0, AN1, AN2, AN3; logic [7:0] sw; //input sliding switches logic [7:0] JA; //output bits to R-2R DAC logic ManConv; initial begin CLK100M = 1'b0; forever #5 CLK100M = ~CLK100M; end initial begin RESET = 1'b1; repeat (10) @(negedge CLK100M); RESET = 1'b0; repeat (1500) @(negedge CLK100M); $stop; end XADC_RTL_Display UUT(.*); endmodule
Timer.sv
//SV module to generate trigger pulses to initiate XADC conversions //clock frequency is 100MHz //default parameter is 10000, outputs a trigger pulse every 100us module Timer #(parameter NUMCLKS = 10000, n = 14) // 'n' needs to accomodate NUMCLKS (input logic Clk, Reset, output logic Pulse); logic [n-1:0] count; always_ff @(posedge Clk, posedge Reset) if (Reset) count <= NUMCLKS - 1; else if (count != 0) count <= count - 1; else count <= NUMCLKS - 1; assign Pulse = (count == 0); //single clk length pulse endmodule : Timer
XADC_Controller.sv
module XADC_Controller(input logic Clk, Reset, trigger, //'trigger' starts conversion input logic ADC_Busy, ADC_EOC, Data_Rdy, output logic Data_En, ADC_SC, input logic [15:0] ADC_Data_in, output logic [15:0] ADC_Data_out, output logic [6:0] ADC_Address); typedef enum logic [3:0] {RES = 0, DADDR, WT_TRIG, SC_HI, SC_LO, WT_EOC, DEN_HI, DEN_LO, WT_DRDY, GET_DATA} state_t; var state_t pstate, nstate; //state register always_ff @(posedge Clk or posedge Reset) if (Reset == 1'b1) pstate <= RES; else pstate <= nstate; //next state always_comb unique case (pstate) RES : nstate = DADDR; DADDR : nstate = WT_TRIG; WT_TRIG : nstate = (trigger == 1'b1)? SC_HI : WT_TRIG; SC_HI : nstate = SC_LO; SC_LO : nstate = WT_EOC; WT_EOC : nstate = (ADC_EOC == 1'b1)? DEN_HI : WT_EOC; DEN_HI : nstate = DEN_LO; DEN_LO : nstate = WT_DRDY; WT_DRDY : nstate = (Data_Rdy == 1'b1)? GET_DATA : WT_DRDY; GET_DATA : nstate = WT_TRIG; default : nstate = RES; endcase //Register Transfer Operations always_ff @(posedge Clk) begin : RTL unique case (pstate) RES : begin Data_En <= 0; ADC_SC <= 0; ADC_Data_out <= '0; ADC_Address <= '0; end DADDR : ADC_Address <= 7'h16; SC_HI : ADC_SC <= 1; WT_EOC : ADC_SC <= 0; DEN_HI : Data_En <= 1; DEN_LO : Data_En <= 0; GET_DATA : ADC_Data_out <= ADC_Data_in; default : ; //do nothing 2/9/16 endcase end : RTL endmodule : XADC_Controller
XADC_RTL_Display.sv
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Create Date: 29.01.2016 17:13:29 // Top-level design file for XADC with RTL Controller and 4 digit hex display //modified September 2016 to include 8 switches as input driving 8 digital outputs to R-2R DAC for testing. ////////////////////////////////////////////////////////////////////////////////// module XADC_RTL_Display( input logic RESET, input logic CLK100M, input logic VAUXP6, //analogue input input logic VAUXN6, output logic CA, //display signals output logic CB, output logic CC, output logic CD, output logic CE, output logic CF, output logic CG, output logic DP, output logic AN0, output logic AN1, output logic AN2, output logic AN3, input logic [7:0] sw, //input sliding switches output logic [7:0] JA, //output bits to R-2R DAC input logic ManConv //push-button manual convert command (BTND) ); //XADC input signals logic DEN, SC; //XADC output signals logic DRDY, BUSY, EOC; //XADC data output logic [15:0] XADC_DO; //XADC address input (selects ADC result register) logic [6:0] DADDR; //display signals logic [15:0] DISP_DATA; logic [3:0] bcdin; logic [1:0] sel; logic Clk, Reset, trigger; logic q0, q1; assign Clk = CLK100M; assign Reset = RESET; //connect switches to DAC assign JA = sw; //instantiation of XADC xadc_wiz_0 ADC1(.convst_in(SC), .daddr_in(DADDR), .dclk_in(Clk), .den_in(DEN), .di_in(), .dwe_in(1'b0), .reset_in(Reset), .vauxp6(VAUXP6), .vauxn6(VAUXN6), .busy_out(BUSY), .channel_out(), .do_out(XADC_DO), .drdy_out(DRDY), .eoc_out(EOC), .eos_out(), .alarm_out(), .vp_in(), .vn_in()); XADC_Controller CON1(.ADC_Busy(BUSY), .ADC_EOC(EOC), .Data_Rdy(DRDY), .Data_En(DEN), .ADC_SC(SC), .ADC_Data_in(XADC_DO), .ADC_Data_out(DISP_DATA), .ADC_Address(DADDR), .*); //for simulation set NUMCLKS to 200 and n to 8 //for implementation use .NUMCLKS(1000000), .n(20) Timer #(.NUMCLKS(200), .n(8)) //100Hz pulse TMR1(.Pulse(trigger), .*); //manual convert start button (use as alternative to above Timer) //always_ff @(posedge Clk) begin : pushbutton // q0 <= ManConv; // q1 <= q0; //end : pushbutton //assign trigger = q0 & ~q1; //end of manual start conversion button //display logic assign DP = 1'b1; //turn off decimal points bcd2seg BCD2SEG1(.*); dispmux DMUX1(.datain(DISP_DATA), .bcd_out(bcdin), .*); //set N = 2 for simulation and 22 for implementation dispcntr #(.N(2)) DCNTR1(.*); endmodule
