VHDL assignment,one week dead line,if u have any doubts,plz let me know,even though i am unware of those,will take help from tutor

module FSM ( input logic clocl,rst, input logic [4:1] sync, output logic RNRZ, RBC,RBE ); typedef enum logic [2:0] {IDLE = 0,SA,SB,SC,SD } state_type; var state_type state; always_ff @(posedge clock,posedge rst) begin : next_state if(rst ==1'b1) state <= IDLE; else unique case(state) IDLE : state <= sync[1]? SA : IDLE ; SA : state <= sync [2] ? SB : (sync[4]? SC : SA ); SB : state <= IDLE; SC : ......... SD : ........ default : state <= IDLE; endcase end : next_state always_ff @ (posedge clock) begin : rtl unique case(state) IDLE : begin RNRZ <= 0 ;RBC <= 1;end SA : RBC <= 0 ; SB : begin RNRZ <= 0 ;RBC <= 1;end SC : begin RNRZ <= 1 ;RBC <= 1;end SD : RBC <= 0 ; endcase end :rtl logic [4:0] qr ; always_ff @ (posedge clock) qr <= {.......}; assign RBE =......; endmodule