EEE 120
Lab 0 Answer Sheet (Remote Lab)
Tutorial: Using Digital
Name: Hrishu Devulapalli_____________________________________________
Instructor/Time: Anna Haywood Tuesday/Thursday 9-10:30AM.____
Date:___________________________
Task 0-0: Visit the Lab
In-person and hybrid students, insert your selfie here. Online students, insert your screenshot here:
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Task 0-1: Build a 2-input XOR gate using AND/OR/NOT gates in Digital
Include a picture of your Digital circuit here:
Please comment on the single biggest issue you were facing when designing the circuit.
The Hardest part of designing the circuit was to plan the logic ahead of time, instead of just using trial
and error to see if it works. I found that using a truth table helped me reach the solution quickly and
without the hassle of testing multiple attempts.
Task 0-3: Export the design and simulate in Verilog
Include a picture of your GTKWave simulation (timing diagram) here:
Please answer the following questions:
1. How do you expect the output of a 2-input XOR gate to behave?
2. What tests did you perform to verify your logic circuit?
3. Did the circuit behave as expected? If no, what was wrong?
Task 0-4: Create a video and submit your report
Record a short video showing your schematic in Digital and your waveforms in GTKWave. Be sure to
show yourself in the video and show your screen. Explain how your circuit works – you need to convince
the grader you did the lab and understand it! Copy and paste the link to your video below. Make sure
the link is working and pointing to the correct video. Remember to include the password if required.
Do NOT upload your video to Canvas. It is recommended that you use Zoom to record to the cloud,
pasting the link and password below. If your circuit is not working as expected, explain in the video how
it is not working and why you think it is not working.
Video Link:
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At the beginning of your recording, say your name and the lab name. Be brief in
your recording. Submit the completed template to Canvas.
Make sure all your files are in the Lab0 directory. Create a zip file of the Lab0
directory. Remember to turn in the zip file AND your completed template on
Canvas!
Do not include the video in the zip file! This makes the file very large and you
run the risk of the zip file not uploading or taking so long to upload that your
submission will be late. Remember that the submission is dated at the time the
upload completes, not when it starts!
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LAB 0: L R G SAB EPORT RADE HEET
Name
NOTE: You submit the zip file in order to show your work.
If the zip file is not submitted you will receive a 0 for this lab!
Instructor Assessment
Grading Criteria Max Points Points Lost
Description of Assigned Tasks, Work Performed & Outcomes Met
Task 0-0: Visit the Lab 5
Task 0-1: Build a 2-input XOR gate using AND/OR/NOT
gates
10
Task 0-3: Export the design and simulate in Verilog 10
Task 0-4: Create a video and submit your report 10
zip file upload (all points lost if missing or incomplete)
Points Lost
Lab Score (35 points total) Late Lab
Lab Score
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