Design a voltage-divider biased common source amplifier with no bypass(JFET)

JFET Equations

Analysis Equations for Voltage Divider Bias:

𝑅𝑖𝑛 = 𝑅𝐺 = 𝑅1||𝑅2

𝑉𝐺𝐺 = ( 𝑅1

𝑅1 + 𝑅2 ) 𝑉𝐷𝐷 = 𝑉𝐺𝑆 + (𝐼𝐷𝑄 ∗ 𝑅𝑆)

𝐼𝐷𝑄 = 𝐼𝐷𝑆𝑆 [1 − ( 𝑉𝐺𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 )]

2

𝑉𝐺𝑆 = 𝑉𝐺𝑆𝑜𝑓𝑓 (1 − √ 𝐼𝐷

𝐼𝐷𝑆𝑆 )

𝑉𝐺𝑆𝑜𝑓𝑓 = 𝑉𝐺𝑆

1−√ 𝐼𝐷

𝐼𝐷𝑆𝑆

To solve the IDQ equation for VGS, it is necessary to arrange it in the form of a quadratic, 𝑎𝑥2 + 𝑏𝑥 + 𝑐 = 0,

and solve for the roots given the quadratic equation, 𝑉𝐺𝑆 = −𝑏±√𝑏2−4𝑎𝑐

2𝑎

𝐼𝐷𝑄 = 𝑉𝐺𝐺−𝑉𝐺𝑆

𝑅𝑆 (Substituting this identity in the IDQ equation)

𝑉𝐺𝐺−𝑉𝐺𝑆

𝑅𝑆 = 𝐼𝐷𝑆𝑆 [1 − (

𝑉𝐺𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 )]

2

The quadratic in terms of the circuit elements will be:

0 = ( 𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆 ∗ 𝑉𝐺𝑆2

𝑉𝐺𝑆(𝑜𝑓𝑓)2 ) − (

2 ∗ 𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆 ∗ 𝑉𝐺𝑆

𝑉𝐺𝑆(𝑜𝑓𝑓) ) + (𝑉𝐺𝑆) + ((𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆) − 𝑉𝐺𝐺)

This will give you 2 solutions for VGS, one which will be unacceptable due to the value of VGS(off),

leaving you with one valid solution.

OR it is necessary to solve the IDQ equation for IDQ, using a substitution for VGS in terms of IDQ and circuit

elements. It is necessary to arrange it in the form of a quadratic, 𝑎𝑥2 + 𝑏𝑥 + 𝑐 = 0 and solve for the roots

given the quadratic equation, 𝐼𝐷𝑄 = −𝑏±√𝑏2−4𝑎𝑐

2𝑎

𝑉𝐺𝑆 = 𝑉𝐺𝐺 − (𝐼𝐷𝑄 ∗ 𝑅𝑆)

𝐼𝐷𝑄 = 𝐼𝐷𝑆𝑆 [1 − ( (𝑉𝐺𝐺 − 𝐼𝐷𝑄 ∗ 𝑅𝑆)

𝑉𝐺𝑆𝑜𝑓𝑓 )]

2

The quadratic in terms of the circuit elements will be:

0 = [( 𝐼𝐷𝑆𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 2 ) ((𝑅𝑆 2𝐼𝐷2) − (2 ∗ 𝑉𝐺𝐺 ∗ 𝑅𝑆 ∗ 𝐼𝐷) + 𝑉𝐺𝐺 2)] − [((

2𝐼𝐷𝑆𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 ) (𝑉𝐺𝐺 − (𝐼𝐷 ∗ 𝑅𝑆))) − 𝐼𝐷] + 𝐼𝐷𝑆𝑆

𝑉𝐷𝐷 = 𝑉𝐷𝑆 + [𝐼𝐷𝑄(𝑅𝐷 + 𝑅𝑆)] or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − [𝐼𝐷𝑄(𝑅𝐷 + 𝑅𝑆)]

𝑔𝑚 (𝑎𝑡 𝑄) = −2 ( 𝐼𝐷𝑆𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 ) [1 − (

𝑉𝐺𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 )]

Analysis Equations for Self-Bias:

𝑅𝑖𝑛 = 𝑅𝐺

𝑉𝐺𝐺 = 0𝑉

To solve the IDQ equation for VGS, it is necessary to arrange it in the form of a quadratic, 𝑎𝑥2 + 𝑏𝑥 + 𝑐 = 0

and solve for the roots given the quadratic equation, 𝑉𝐺𝑆 = −𝑏±√𝑏2−4𝑎𝑐

2𝑎

𝐼𝐷𝑄 = − ( 𝑉𝐺𝑆

𝑅𝑆 )

− ( 𝑉𝐺𝑆

𝑅𝑆 ) = 𝐼𝐷𝑆𝑆 [1 − (

𝑉𝐺𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 )]

2

(Substituting for IDQ in IDQ equation)

The quadratic in terms of the circuit elements will be:

0 = ( 𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆 ∗ 𝑉𝐺𝑆2

𝑉𝐺𝑆(𝑜𝑓𝑓)2 ) − (

2 ∗ 𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆 ∗ 𝑉𝐺𝑆

𝑉𝐺𝑆(𝑜𝑓𝑓) ) + (𝑉𝐺𝑆) + (𝐼𝐷𝑆𝑆 ∗ 𝑅𝑆)

This will give you 2 solutions for VGS, one which will be unacceptable due to the value of VGS(off),

leaving you with one valid solution.

OR it is necessary to solve the IDQ equation for IDQ, using a substitution for VGS in terms of IDQ and circuit

elements. It is necessary to arrange it in the form of a quadratic, 𝑎𝑥2 + 𝑏𝑥 + 𝑐 = 0 and solve for the roots

given the quadratic equation, 𝐼𝐷𝑄 = −𝑏±√𝑏2−4𝑎𝑐

2𝑎

𝑉𝐺𝑆 = −(𝐼𝐷𝑄 ∗ 𝑅𝑆)

𝐼𝐷𝑄 = 𝐼𝐷𝑆𝑆 [1 − ( (−𝐼𝐷𝑄∗𝑅𝑆)

𝑉𝐺𝑆𝑜𝑓𝑓 )]

2

(Substituting for VGS in the IDQ equation)

The quadratic in terms of the circuit elements will be:

0 = ( 𝐼𝐷𝑆𝑆(𝐼𝐷 ∗ 𝑅𝑆)2

𝑉𝐺𝑆𝑜𝑓𝑓 2 ) + (

2𝐼𝐷𝑆𝑆 ∗ 𝐼𝐷 ∗ 𝑅𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 − 𝐼𝐷) + 𝐼𝐷𝑆𝑆

𝑉𝐷𝐷 = 𝑉𝐷𝑆 + [𝐼𝐷𝑄(𝑅𝐷 + 𝑅𝑆)] or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − [𝐼𝐷𝑄(𝑅𝐷 + 𝑅𝑆)]

𝑔𝑚 (𝑎𝑡 𝑄) = −2 ( 𝐼𝐷𝑆𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 ) [1 − (

𝑉𝐺𝑆

𝑉𝐺𝑆𝑜𝑓𝑓 )]

Common Source w/Full Bypass Capacitor: (Analogous to CE w/FBP)

𝑅𝑎𝑐 = (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑)

𝑅𝑑𝑐 = 𝑅𝐷 + 𝑅𝑆

𝐴′𝑉 = −𝑔𝑚 (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑)

𝐴𝑉𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑖𝑛 + 𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )

𝐴𝑖 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑙𝑜𝑎𝑑 )

Common Source w/No Bypass Capacitor: (Analogous to CE w/NBP)

𝑅𝑎𝑐 = (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑) + 𝑅𝑆

𝑅𝑑𝑐 = 𝑅𝐷 + 𝑅𝑆

𝐴′𝑉 = − 𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑

𝑅𝑆 + ( 1

𝑔𝑚 )

𝐴𝑉𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑖𝑛 + 𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )

𝐴𝑖 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑙𝑜𝑎𝑑 ) = −

𝑅𝐺 ∗ 𝑅𝐷

[(𝑅𝑆 + ( 1

𝑔𝑚 )) (𝑅𝐷 + 𝑅𝑙𝑜𝑎𝑑)]

Common Source w/Partial Bypass Capacitor:

𝑅𝑎𝑐 = (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑) + 𝑅𝑆1

𝑅𝑑𝑐 = 𝑅𝐷 + 𝑅𝑆1 + 𝑅𝑆2

𝐴′𝑉 = − 𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑

𝑅𝑆1 + ( 1

𝑔𝑚 )

𝐴𝑉𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑖𝑛 + 𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )

𝐴𝑖 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑙𝑜𝑎𝑑 )

Common Drain (Source Follower): (Analogous to CC, A’V < +1, Current Amplifier)

𝑅𝑎𝑐 = (𝑅𝑆\\𝑅𝑙𝑜𝑎𝑑)

𝑅𝑑𝑐 = 𝑅𝑆

𝐴′𝑉 = (𝑅𝑆\\𝑅𝑙𝑜𝑎𝑑)

[(𝑅𝑆\\𝑅𝑙𝑜𝑎𝑑) + ( 1

𝑔𝑚 )]

𝐴𝑉𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑖𝑛 + 𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )

𝐴𝑖 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑙𝑜𝑎𝑑 ) = (

𝑅𝑆

𝑅𝑆 + 𝑅𝑙𝑜𝑎𝑑 ) (

𝑅𝐺

[(𝑅𝑆\\𝑅𝑙𝑜𝑎𝑑) + ( 1

𝑔𝑚 )]

Common Drain w/Partial Bypass Arrangement:

𝐴′𝑉 = 𝑅𝑆1\\𝑅𝐿

[(𝑅𝑆1\\𝑅𝐿) + ( 1

𝑔𝑚 )]

𝐴𝑖 = [ 𝑅𝑆1

𝑅𝑆1 + 𝑅𝐿 ] [

𝑅𝐺

(𝑅𝑆1\\𝑅𝐿) + ( 1

𝑔𝑚 )

]

Common Gate: (Analogous to CB)

𝑅𝑖𝑛 = 𝑅𝑆\\(1/𝑔𝑚)

𝑅𝑎𝑐 = (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑) + 𝑅𝑆

𝑅𝑑𝑐 = 𝑅𝐷 + 𝑅𝑆

𝐴′𝑉 = +𝑔𝑚 (𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑)

𝐴𝑉𝑜𝑣𝑒𝑟𝑎𝑙𝑙 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑖𝑛 + 𝑅𝑠𝑜𝑢𝑟𝑐𝑒 )

𝐴𝑖 = 𝐴′𝑉 ( 𝑅𝑖𝑛

𝑅𝑙𝑜𝑎𝑑 ) = (

(𝑅𝐷 ∗ 𝑅𝑆)

(𝑅𝐷 + 𝑅𝑙𝑜𝑎𝑑)(𝑅𝑆 + ( 1

𝑔𝑚 ))

)

DESIGN EQUATIONS:

𝑅1 = 𝑅𝐺

[1 − ( 𝑉𝐺𝐺 𝑉𝐷𝐷

)]

𝑅2 = 𝑅𝐺 ∗ 𝑉𝐷𝐷

𝑉𝐺𝐺

DESIGN PROCEDURE: (Common Source – but this is ‘general’ procedure for all types as well, but other

known equations may be necessary.

1. A Q-point will be given or selected

a. This should identify VGSQ, IDQ, and VDSQ (at mid-point, IDQ = IDSS/2, VGSQ = 0.3VGSoff, and

VDSQ = VDD/2)

2. Once Q-point is known, Solve for (RD + RS) from VDD loop equation

3. Use gain equation to solve for RD (set up another quadratic for this solution – one root will be valid)

4. Calculate RS

5. Calculate VGG

6. Evaluate VGG – if VGG is the same polarity as VDD (positive for n-channel) and VGSQ is opposite in

polarity, then proceed to R1 and R2 calculations

7. Evaluate VGG – if VGG is opposite in polarity to VDD (negative for n-channel), Let the circuit

arrangement be changed to Self-Biased with partial bypass arrangement or change the Q-point if

allowable. You will recalculate RS1, RS2, and RD.

8. Recalculate RS: 𝑉𝐺𝐺 = 0𝑉 = 𝑉𝐺𝑆𝑄 + [𝐼𝐷𝑄(𝑅𝑆1 + 𝑅𝑆2)] and

(𝑅𝑆1 + 𝑅𝑆2) = −( 𝑉𝐺𝑆𝑄

𝐼𝐷𝑄 )

9. Recalculate RD: 𝑅𝐷 = [(𝑅𝐷 + 𝑅𝑆)𝑜𝑟𝑖𝑔𝑖𝑛𝑎𝑙] − (𝑅𝑆1 + 𝑅𝑆2)

10. Calculate RS1 from gain equation: 𝑅𝑆1 = [− 𝑅𝐷\\𝑅𝑙𝑜𝑎𝑑

𝐴′𝑉 ] − (

1

𝑔𝑚 )

11. Calculate RS2: 𝑅𝑆2 = (𝑅𝑆𝑡𝑜𝑡𝑎𝑙 − 𝑅𝑆1)

12. Determine R1: 𝑅1 = 𝑅𝑖𝑛 = 𝑅𝐺