Design a voltage-divider biased common source amplifier with no bypass(JFET)

design a voltage-divider biased common source amplifier with no bypass to the following specifications: Av_(overall) = -3, Rsrc = 30 kΩ, Rin = 300kΩ, RL = 1.5 kΩ, VGS(off) = -3V, IDSS = 15 mA, VDD = 24V Design for midpoint operation. Show all calculations and draw the circuit including resister valus.

*Note: attached are the equations needed

please provide a stip by stip solotion so I can understand