Comprehensive Practice Material: The Exclusive OR (XOR)
Operation
Course: COMP 222 - Introduction to Computer Science/Digital Logic
Institution: California State University, Northridge (CSUN)
Topic: Boolean Exclusive OR (
⊕
) / Logical Inequality
SECTION A: Foundational Concepts and Algebraic Identities
This section tests your understanding of the basic definition, truth table, and core
algebraic laws specific to the XOR operation.
Problem A.1: Basic Definition and Truth Table
If we define the XOR operation as the Logical Inequality, where the output
Y
is TRUE
if and only if the inputs
A
and
B
are different:
a) State the resulting output
Y
for the following input combinations:
1.
A=1, B=0⇒Y=?
2.
A=1, B=1⇒Y=?
b) Using standard Boolean algebra notation, write the Sum-of-Products (SOP)
expression for
Y=A⊕B
.
Problem A.2: The Complement Function (XNOR)
The Exclusive NOR (XNOR) function, denoted
A⊙B
, is the complement of XOR.
a) State the logical condition under which
A⊙B
is TRUE.
b) Write the SOP expression for
A⊙B
.
c) Explain the primary architectural role of the XNOR gate (i.e., what is it designed to
check?).
Problem A.3: Applying Identity and Complement Properties
Using the algebraic laws specific to the XOR operation, simplify the following
expressions without resorting to the full SOP expansion:
a)
Ya=A⊕0
b)
Yb=A⊕A
c)
Yc=A⊕1
d)
Yd=( A⊕1)⊕0
Problem A.4: Associativity and Commutativity
The XOR operation is both associative and commutative. Use this property to
simplify the following 4-input expression,
Y=P⊕Q⊕P⊕R
, by grouping terms.
Problem A.5: Single-Gate Toggling
You are given a single XOR gate with inputs
A
and
B
. You want to use input
B
as a
Control Signal (C) to either pass
A
through unchanged or invert
A
.
a) Write the logical output
Y
in terms of
A
when
C=0
.
b) Write the logical output
Y
in terms of
A
when
C=1
.
c) Based on your answers, explain why the XOR gate is often called a "Controlled
Inverter."
SECTION B: Gate Level Implementation and Simplification
This section focuses on manipulating expressions containing XOR, converting
between forms, and understanding gate-level requirements.
Problem B.1: Full Expansion and Simplification
Expand the following expression fully into its standard SOP form, and then simplify
the resulting expression using standard Boolean algebra laws:
Y=( A⊕B)+ A
Problem B.2: XNOR Expansion and De Morgans Law
You are given the XNOR expression
Y=A⊙B
.
a) Expand
Y
into its standard SOP form (as found in Problem A.2).
b) Prove that the resulting SOP expression is equivalent to the negation of the
standard XOR SOP expression,
A B+A B
―
, by applying De Morgans Law to the negated
XOR form. (Hint: Use the principle of duality and the complement laws
X+X=1
and
X⋅X=0
).
Problem B.3: The Power of Involution
Simplify the following complex expression by first expanding the inner XOR term
and then applying algebraic laws. Focus on removing redundant terms.
Y=A⊕B
―
⋅(A+B)
Problem B.4: The Forbidden Coincidence
Consider the expression
Y=( A⊕B)⋅(A⊙B)
.
a) Expand
Y
into its simplest SOP form.
b) Explain the logical significance of the result in the context of digital circuit design.
Problem B.5: Gate Level Minimization
Given the function
Y=A⊕B⊕A
:
a) Simplify the expression algebraically to its minimum form.
b) If you were forced to build the unsimplified expression using only 2-input NAND
gates, estimate the total number of gates required for the three-input XOR
operation,
A⊕B⊕A
. (Self-reflection required: How many NAND gates are typically
required to build a 2-input XOR, and how does the associativity help/hurt?)
SECTION C: Arithmetic and Adder Circuits
This section explores the critical role of XOR in computer arithmetic and the
fundamental building blocks of the Arithmetic Logic Unit (ALU).
Problem C.1: The Half-Adder Function
A Half-Adder takes two single-bit inputs,
A
and
B
, and produces two outputs: Sum (
S
) and Carry-out (
Cout
).
a) Identify the specific Boolean operator required for the Sum (
S
) output.
b) Write the function for the Carry-out (
Cout
) output.
c) Explain the limitation of the Half-Adder that necessitates the use of the Full-
Adder.
Problem C.2: The Full-Adder Sum Logic
The Sum (
S
) output of a Full-Adder (FA) is given by
S=A⊕B⊕C¿
, where
C¿
is the
carry-in.
a) If
A=1, B=1, C¿=1
, calculate the Sum
S
and the Carry-out
Cout
.
b) Explain why the XOR operation perfectly models the concept of "binary addition
without carry."
Problem C.3: Building a 4-Bit Ripple-Carry Adder
A 4-bit Ripple-Carry Adder is built using four cascaded Full-Adders (
F A0, F A1, F A2, F A3
).
a) If
C¿
to
F A0
is 0, and the two 4-bit numbers being added are
A=10012
and
B=01102
, write out the
S
output of
F A1
(the second Full-Adder stage).
b) From a timing perspective, why does the extensive use of XOR gates in the Sum
path (
S=A⊕B⊕C¿
) contribute significantly to the overall worst-case delay of the
Ripple-Carry Adder?
Problem C.4: Controlled Subtraction
The 2s Complement method allows subtraction (
X −Y
) to be performed by addition
(
X+(−Y )
). The Ones Complement (NOT) is the first step.
Explain how a multiplexer (MUX) and an array of XOR gates can be used in the input
path of a standard 4-bit adder to select between addition and subtraction mode,
based on a single control signal
Sctrl
.
Problem C.5: XNOR as a Magnitude Comparator
An
N
-bit equality comparator determines if two
N
-bit numbers,
A
and
B
, are
identical.
a) Write the simplified Boolean expression for the equality comparison of two single
bits,
E
, using the XNOR function.
b) Write the final expression for the total equality
Etotal
of two 4-bit numbers,
A3A2A1A0
and
B3B2B1B0
. What kind of basic logic gate must combine the individual
bit results to yield
Etotal
?
SECTION D: Parity and Error Detection
This section examines the multi-input property of XOR and its fundamental
application in error-checking systems.
Problem D.1: Odd vs. Even Parity
The multi-input XOR gate acts as an odd parity checker.
a) Define the output condition (TRUE or FALSE) of a 5-input XOR gate when the
number of inputs is even.
b) Define the output condition (TRUE or FALSE) of a 5-input XOR gate when the
number of inputs is odd.
c) What simple gate function must be applied to the output of an
N
-input XOR gate
to convert it into an Even Parity Generator?
Problem D.2: Parity Generation
A system uses Even Parity for 8-bit data transmission. The data byte is
D=11010010
.
a) Calculate the value of the parity bit
P
.
b) Write the full 9-bit transmitted word (Data + Parity).
Problem D.3: Parity Checking
An 8-bit data word
D=10101011
is transmitted using Odd Parity. The calculated
parity bit
P
is sent along with it. The receiver receives the 9-bit word
R=101010111
.
a) Determine the expected value of the parity bit
P
based on the data
D
.
b) Based on the received word
R
, does the parity check indicate an error?
Problem D.4: Failure Mode of XOR Parity
A 10-bit data word is transmitted using Even Parity. Due to noise, two distinct bits
flip their state during transmission.
a) Will the XOR parity checker at the receiver signal an error (Output = 1)?
b) Explain why the XOR parity mechanism fails to detect an error in this specific
scenario.
Problem D.5: Cascading for Parity Generation
You only have 2-input XOR gates. You need to build a circuit that generates the
parity bit for a 7-bit data word (
D6
down to
D0
).
a) Draw the required structure, showing the minimum number of 2-input XOR gates
required.
b) Identify the total propagation delay path in terms of the number of XOR gates.
SECTION E: Programming and Bitwise Logic
This section explores the use of the XOR operator (^) in programming for
manipulation, optimization, and simple cryptography.
Problem E.1: Bitwise XOR vs. Logical XOR
In a C-style language, distinguish between the operation and result of the bitwise
XOR (^) and the logical NOT (!) for the following integer values, assuming an 8-bit
integer:
a)
A=6
(binary
00000110
)
b)
B=0
(binary
00000000
)
Calculate:
AXOR5
! A
BXOR 1
! B
Problem E.2: The XOR Swap (Detailed Trace)
Trace the values of integer variables
X
and
Y
through the three steps of the XOR
swap algorithm, starting with
X=10
(binary
10102
) and
Y=5
(binary
01012
).
X=X⊕Y
Y=X⊕Y
X=X⊕Y
What is the final value of
X
and
Y
?
Problem E.3: Controlled Bit Toggling
A programmer wants to write a function that flips the state of only the three least
significant bits (LSBs) of an 8-bit integer variable
DATA
, while leaving the other five
bits untouched.
a) What specific 8-bit mask value (
M
) must be used? Give your answer in both
binary and decimal.
b) Write the single line of code, using the bitwise XOR operator, to perform this
operation.
Problem E.4: Simple XOR-based Encryption
A 4-bit plaintext message
P=1101
is encrypted using a 4-bit key
K=0110
.
a) Calculate the resulting 4-bit ciphertext
C
.
b) Show the calculation required to decrypt the ciphertext
C
using the same key
K
to retrieve the original plaintext
P
.
Problem E.5: Bitwise Condition Check
You are tasked with checking if the 4th bit (index 3, starting from 0) of an 8-bit
integer
DATA
is currently set (equal to 1). If it is set, you want to clear (set to 0) the
4th bit and leave all others unchanged.
a) What bitwise operation is generally used to check if a specific bit is set?
b) What bitwise operation (AND, OR, or XOR) must be used, along with an
appropriate mask, to clear the bit only if it is currently set, and to leave it unchanged
only if it is currently cleared? Explain your choice.
ANSWER KEY AND DETAILED EXPLANATIONS
The following section provides comprehensive answers and step-by-step
explanations for all practice problems. Review these carefully to reinforce the
concepts covered in the study guide.
SECTION A: Foundational Concepts and Algebraic Identities - Solutions
A.1: Basic Definition and Truth Table
a)
A=1, B=0⇒Y=1
(Inputs are different)
A=1, B=1⇒Y=0
(Inputs are the same)
b)
Y=A B+A B
A.2: The Complement Function (XNOR)
a)
A⊙B
is TRUE if and only if the inputs
A
and
B
are the same (equal).
b)
A⊙B=A B+AB
c) The XNOR gate is primarily used as an Equality Comparator. It outputs HIGH (1)
whenever the two input bits match.
A.3: Applying Identity and Complement Properties
a)
Ya=A⊕0=A
(Identity Law: XOR with 0 yields the original variable)
b)
Yb=A⊕A=0
(Self-Annihilation Law: XOR with self always yields 0)
c)
Yc=A⊕1=A
(Complement Law: XOR with 1 yields the complement of the
variable)
d)
Yd=( A⊕1)⊕0=A⊕0=A
(First applies Complement Law, then Identity Law)
A.4: Associativity and Commutativity
Y=P⊕Q⊕P⊕R
Group the identical terms using the Commutative Law:
Y=(P⊕P)⊕Q⊕R
Apply the Self-Annihilation Law (
P⊕P=0
):
Y=0⊕Q⊕R
Apply the Identity Law (
0⊕Q=Q
):
Y=Q⊕R
A.5: Single-Gate Toggling
The output is
Y=A⊕C
.
a) When
C=0
:
Y=A⊕0=A
(The signal
A
passes through unchanged.)
b) When
C=1
:
Y=A⊕1=A
(The signal
A
is inverted.)
c) The XOR gate is a "Controlled Inverter" because a single control signal (
C
)
determines its functionality: when
C=0
, it acts as a non-inverting buffer; when
C=1
, it acts as an inverter (NOT gate).
SECTION B: Gate Level Implementation and Simplification - Solutions
B.1: Full Expansion and Simplification
Y=( A⊕B)+ A
Expand the XOR term:
Y=( A B+A B)+ A
Apply the Associative Law and Commutative Law:
Y=A+A B+A B
Use the Absorption Law variation (
X+X Y =X+Y
) where
X=A
and
Y=B
for the
first two terms:
Y=A+A B
Apply the Absorption Law variation again:
Y=A+B
Result:
Y=A+B
.
B.2: XNOR Expansion and De Morgans Law
a) SOP form for XNOR:
Y=A B+AB
b) Proof of Equivalence:
Start with the negation of the XOR SOP form:
Y=A B+A B
―
Apply De Morgans Law (
X+Y
―
=X Y
), where
X=A B
and
Y=A B
:
Y=( A B
―
)⋅(A B
―
)
Apply De Morgans Law again to the terms inside the parentheses:
Y=( A
―
+B)⋅(A+B
―
)
Apply the Involution Law (
A
―
=A
and
B
―
=B
):
Y=( A+B)⋅(A+B)
Expand the expression by multiplying (FOIL method):
Y=A A+AB+B A +B B
Apply the Complement Law (
A A=0
and
B B=0
):
Y=0+AB+A B+0
Result:
Y=AB+A B
, which is the SOP for XNOR. (Proven)
B.3: The Power of Involution
Y=A⊕B
―
⋅(A+B)
Recognize that
A⊕B
―
=A⊙B=A B+AB
.
Y=( A B+AB)⋅(A+B)
Distribute the
(A+B)
term:
Y=( A B⋅A)+(A B ⋅B)+( AB⋅A)+(AB ⋅B)
Apply the Complement Law (e.g.,
B⋅B=0
and
A⋅A=0
) and the Idempotence Law
(e.g.,
A⋅A=A
and
B⋅B=B
):
Y=0+0+AB+AB
Apply the Idempotence Law (
AB+AB=AB
):
Result:
Y=AB
.
B.4: The Forbidden Coincidence
Y=( A⊕B)⋅(A⊙B)
The expression requires that the XOR function is TRUE AND the XNOR function is
TRUE simultaneously.
a) Expand and simplify:
Y=( A B+A B)⋅(A B+AB)
When you multiply these terms, you will find every resulting term contains an
identity that resolves to 0 (e.g.,
(A B)⋅(A B)
contains
B B=0
).
Y=0
b) Logical Significance: The result is always 0 (FALSE). This confirms that a set of
inputs can never satisfy the conditions for XOR (inputs are different) AND XNOR
(inputs are the same) simultaneously. They are mutually exclusive functions. The
circuit acts as a permanent ground connection.
B.5: Gate Level Minimization
a) Simplify
Y=A⊕B⊕A
:
Y=( A⊕A)⊕BY =0⊕B
Result:
Y=B
.
b) Gate Estimation:
A 2-input XOR gate requires 4 NAND gates (
A AB
¿
⋅B AB
¿
).
The expression is
Y=( A⊕B)⊕A
. This requires two 2-input XOR stages.
Total NAND gates required:
4 (for A⊕B¿+4 (for the final XOR)=8 NAND gates
.
Self-Reflection: The associativity requires us to use two separate XOR gates, even
though the final result simplifies to a simple wire (
B
). This demonstrates that
hardware is built based on the unsimplified logical structure unless pre-optimized.
SECTION C: Arithmetic and Adder Circuits - Solutions
C.1: The Half-Adder Function
a) The Sum (
S
) output requires the Exclusive OR (XOR) operator. (
S=A⊕B
)
b) The Carry-out (
Cout
) output requires the AND operator. (
Cout=A⋅B
)
c) Limitation: The Half-Adder has no Carry-in (
C¿
) input. This means it can only add
the two least significant bits (LSBs) of two multi-bit numbers and cannot be used for
any subsequent bit position, which requires the carry from the previous stage. The
Full-Adder solves this by including the
C¿
input.
C.2: The Full-Adder Sum Logic
a) Inputs:
A=1, B=1, C¿=1
.
Sum
S=A⊕B⊕C¿=1⊕1⊕1=0⊕1=1
.
Carry-out
Cout=AB +C¿(A⊕B)
.
Cout=(1⋅1)+1⋅(1⊕1)=1+1⋅0=1+0=1
Result:
S=1, Cout=1
. (This represents
1+1+1=310 =112
)
b) Explanation: Binary addition without carry is equivalent to checking for
odd/even. In binary,
1+1=0
(with a carry),
1+0=1
, and
0+0=0
. The Sum bit is 1
only when there is an odd number of 1s in the inputs. The XOR function, by
definition, outputs 1 if and only if there is an odd number of TRUE inputs, perfectly
modeling this operation.
C.3: Building a 4-Bit Ripple-Carry Adder
We are adding
A=10012
and
B=01102
. We need to trace the calculation up to
F A1
.
Stage
F A0
(LSB):
A0=1, B0=0,C¿=0
.
S0=1⊕0⊕0=1Cout , 0=1⋅0+0⋅(1⊕0)=0+0=0
C¿
for
F A1
is
Cout ,0=0
.
Stage
F A1
(Second Bit):
A1=0, B1=1, C¿=0
.
S1=A1⊕B1⊕C¿=0⊕1⊕0=1
Result: The
S
output of
F A1
is
S1=1
.
b) Worst-Case Delay: The Sum output of any Full-Adder stage (
S=A⊕B⊕C¿
) is
dependent on the
C¿
from the previous stage. Since
C¿
is dependent on the XOR
output of the previous stage, and the Sum path is already 2 levels deep (two XOR
gates) to compute the sum, the logic path for
S
is long. The "ripple" effect means that
the final Sum bit,
S3
, must wait for
Cout ,0
, then
Cout ,1
, then
Cout ,2
to be fully resolved.
Because XOR gates add a significant propagation delay, this cascading dependency
(known as the Carry Propagation Delay) becomes the major bottleneck in the
adders speed.
C.4: Controlled Subtraction
The control signal is
Sctrl
(
0=¿
Addition,
1=¿
Subtraction). To perform subtraction
X −Y
, we must generate
X+Y
―
+1
.
Ones Complement Generation (
Y
―
): The
Y
operand must be selectively inverted. An
array of XOR gates is placed at the input of the adders
B
terminals (
B0
to
B3
).
For each bit
Bi
: Input is
Yi⊕Sctrl
.
If
Sctrl=0
:
Yi⊕0=Yi
(Passes
Y
unchanged for addition).
If
Sctrl=1
:
Yi⊕1=Y
―
i
(Inverts
Y
for subtraction).
Adding the "+1": The
Sctrl
signal is directly connected to the Carry-in (
C¿
) of the LSB
Full-Adder (
F A0
).
If
Sctrl=0
:
C¿=0
(Standard addition).
If
Sctrl=1
:
C¿=1
(Adds the required
+1
for the 2s complement).
The XOR gates are used as "Controlled Inverters" to conditionally perform the Ones
Complement.
C.5: XNOR as a Magnitude Comparator
a) The equality comparison
E
of two bits
A
and
B
is TRUE if they are the same. This
is the definition of XNOR:
E=A⊙Bor E=A⊕B
―
b) For the two 4-bit numbers to be totally equal, all corresponding bits must be
equal. We first perform four parallel XNOR operations to check each bit pair (
E3, E2, E1, E0
). Then, we must combine these four results.
The final expression is:
Etotal =E3⋅E2⋅E1⋅E0
The individual bit results must be combined using an AND gate (specifically, a 4-
input AND gate).
SECTION D: Parity and Error Detection - Solutions
D.1: Odd vs. Even Parity
a) Output condition of a 5-input XOR gate when the number of inputs is even: FALSE
(0). (Because XOR checks for odd parity).
b) Output condition of a 5-input XOR gate when the number of inputs is odd: TRUE
(1).
c) To convert an
N
-input XOR gate (Odd Parity Generator) into an Even Parity
Generator, you must apply a NOT gate (inverter) to the XOR output. (If the count of
1s is odd, XOR outputs 1; NOT outputs 0, indicating incorrect even parity.)
D.2: Parity Generation
Data byte
D=11010010
.
a) Calculate the XOR sum of the data bits to find the Odd Parity bit:
Podd=1⊕1⊕0⊕1⊕0⊕0⊕1⊕0=0
Since the system uses Even Parity, the parity bit must be the complement of
Podd
:
P=P
―
odd=0
―
=1
(Alternatively: The data has four s (even count). To make the total count of 1s even,
the parity bit must be 0. Wait, I made a mistake in the XOR calculation. Lets
recalculate the XOR sum of the data:
1⊕1=0
,
0⊕0=0
,
0⊕1=1
,
1⊕0=1
. The count
of 1s in the data is 4 (even). The XOR sum of 4 bits is 0. If we want Even Parity, the
total number of 1s in the transmitted word must be even. Since the data has 4 s, the
parity bit
P
must be 0 to maintain an even count.)
Recalculating the XOR sum for
D=11010010
:
1⊕1⊕0⊕1⊕0⊕0⊕1⊕0=0
.
The count of 1s in the data is 4 (Even).
If we use Odd Parity:
P=1
(Total 1s = 5, Odd).
If we use Even Parity:
P=0
(Total 1s = 4, Even).
Result:
P=0
.
b) Full 9-bit transmitted word (Data + Parity):
110100100
.
D.3: Parity Checking
Data
D=10101011
(Count of 1s = 5, Odd). System uses Odd Parity.
a) The expected parity bit
P
must make the total count of 1s odd. Since the data is
already odd (5),
P
must be 0.
Expected
P=0
.
b) Received word
R=101010111
. (Total Count of 1s = 6, Even).
Feed the received word into the Odd Parity checker (XOR chain):
C=1⊕0⊕1⊕0⊕1⊕0⊕1⊕1⊕1C=(XOR sum of 6 ones)=0
The checker outputs
C=0
. Since this is an Odd Parity system, an output of 0 means
the total count is even, which is an error.
Result: Yes, the parity check indicates an error. (The output should have been 1 for
correct odd parity).
D.4: Failure Mode of XOR Parity
a) Will the XOR parity checker signal an error? No.
b) Explanation: The XOR parity checker only monitors the mod-2 sum of the 1s (i.e.,
whether the total count is odd or even). If a double-bit error occurs (two bits flip),
the total number of 1s either increases by 2, decreases by 2, or stays the same. In all
cases, the original parity (odd or even) is preserved. For instance, if a 0 and a 1 both
flip, they become a 1 and a 0, maintaining the total count. Since the total count of 1s
remains an even number of deviations, the XOR checker outputs 0 (no error
detected), causing the error to go unnoticed.
D.5: Cascading for Parity Generation
a) Structure: To calculate the XOR sum of 7 inputs, we must cascade 2-input XOR
gates in a tree-like structure.
Level 1: 3 XOR gates (calculate
D0⊕D1
,
D2⊕D3
,
D4⊕D5
) + 1 input
D6
Level 2: 2 XOR gates (combine the results of Level 1)
Level 3: 1 XOR gate (final result)
Result: Minimum number of 2-input XOR gates required is
3+2+1=6
gates.
b) Propagation Delay: The longest path goes through the greatest number of gates
from input to output. This circuit has a maximum of 3 XOR gates in series.
SECTION E: Programming and Bitwise Logic - Solutions
E.1: Bitwise XOR vs. Logical NOT
a)
A=6(000001102)
AXOR5
:
000001102⊕000001012=000000112
. Result: 3 (Bitwise operation).
! A
: Since
A
is non-zero (6),
! A
is equivalent to
!TRUE
. Result: 0 (Logical operation).
b)
B=0(000000002)
3.
BXOR 1
:
000000002⊕000000012=000000012
. Result: 1 (Bitwise operation).
4.
! B
: Since
B
is zero (0),
! B
is equivalent to
! FALSE
. Result: 1 (Logical
operation).
E.2: The XOR Swap (Detailed Trace)
Start:
X=10(10102), Y =5(01012)
X=X⊕Y
:
X=10102⊕01012=11112
. (
X=15
)
Current state:
X=15 ,Y =5
Y=X⊕Y
:
Y=11112⊕01012=10102
. (
Y=10
, which is the original value of
X
)
Current state:
X=15 ,Y =10
X=X⊕Y
:
X=11112⊕10102=01012
. (
X=5
, which is the original value of
Y
)
Current state:
X=5,Y =10
Final Value:
X=5
and
Y=10
. The values have been successfully swapped.
E.3: Controlled Bit Toggling
a) To flip the three LSBs (bits 0, 1, 2), the mask must have 1s in those positions and
0s everywhere else.
Binary Mask (
M
):
000001112
Decimal Mask (
M
):
4+2+1=7
.
b) The code uses XOR because
A⊕1=A
(flips) and
A⊕0=A
(no change).
DATA = DATA ^ 7; // or DATA ^= 7;
E.4: Simple XOR-based Encryption
a) Calculate the ciphertext
C
:
C=P⊕KC=11012⊕01102=10112
Result: Ciphertext
C=1011
.
b) Decryption calculation:
P=C⊕KP=10112⊕01102=11012
Result: Plaintext
P=1101
, successfully decrypted.
E.5: Bitwise Condition Check
a) The bitwise operation generally used to check if a specific bit is set is the Bitwise
AND (
¿
) operation with a mask containing a 1 at that position. If the result is non-
zero, the bit was set.
b) The operation must be Bitwise XOR (
∧
).
The mask (
M
) for the 4th bit (index 3) is
000010002
(decimal 8).
The required operation is DATA = DATA ^ 8; (or DATA ^= 8;).
Explanation: The XOR operation is used because of its toggling property.
Case 1: Bit is set (1).
1⊕1=0
. The bit is cleared (set to 0).
Case 2: Bit is cleared (0).
0⊕1=1
. The bit is toggled (set to 1).
Correction/Refinement: The prompt states: "If it is set, you want to clear (set to 0)
the 4th bit and leave all others unchanged." The simple XOR command above always
flips the bit. If the bit was 0, it becomes 1, which violates the requirement to leave it
unchanged if it was already cleared.
Therefore, you must use a conditional structure derived from the AND check:
Check: if (DATA & 8)
Clear (If TRUE): DATA = DATA & (~8); (Use AND with a mask of all 1s except at the
target bit).
