CSUN Technical Study Notes: Memory (RAM/ROM) – The
Storage Substrate of Computation
Topic: Storing Instructions and Data: Understanding RAM and ROM and the Memory
Hierarchy
Context: Von Neumann Architecture, CPU-Memory Interaction, and System
Performance
Part I: A Student’s Conceptualization of Memory
My primary insight into the role of computer memory is its absolute centrality to the
Von Neumann architecture, the foundational design principle of almost every
modern computing device. In this model, the CPU is the brain, the Arithmetic Logic
Unit (ALU) is the calculator, and the Control Unit (CU) is the conductor. But memory
is the workspace and the library combined. It is the unified, temporary dwelling
place for both the instructions that tell the CPU what to do and the data upon which
those instructions operate. This unification is what distinguishes the Von Neumann
architecture and, consequently, memorys role is not passive—it is the dynamic,
active medium through which the entire computational process is channeled.
The distinction between Random Access Memory (RAM) and Read-Only Memory
(ROM) is not merely a technical classification; it represents the fundamental
dichotomy between the dynamic and volatile execution environment (RAM) and the
static, persistent, and foundational control logic (ROM). RAM is the chaotic,
temporary scratchpad where the operating system, applications, and current data
reside and are actively manipulated. It is volatile, reflecting its transient nature,
designed for speed and constant change. ROM, conversely, represents the
immutable laws of the system—the boot-up sequence, the foundational firmware—
which must persist even when power is removed. Grasping the physical and logical
reasons for this volatile/non-volatile separation is essential to understanding the
system’s stability and functionality, especially during the critical power-on
sequence. This entire structure of storage forms the indispensable foundation for
every operation managed by the Control Unit.
Part II: Core Definitions and the Function of Memory
Memory, in the context of the CPU, refers to the main storage area accessible
directly by the processor. Its primary purpose is to hold programs (instructions)
and their required data during execution.
1. The Abstract View: Address and Word Size
From the CPUs perspective, memory is a linear, ordered array of storage locations.
Address Space: Every memory location is uniquely identified by an address. The size
of the address bus determines the maximum size of the addressable memory space.
For example, a CPU with a 32-bit address bus can theoretically address
232
unique
memory locations (approximately 4 Gigabytes). Modern systems use 64-bit
addressing, enabling vast memory spaces.
Word Size and Byte-Addressability: The most basic unit of addressable memory is
the byte (8 bits). Most modern computer architectures are byte-addressable,
meaning each individual byte has its own unique address. However, the CPU often
accesses memory in larger blocks called words (typically 32 or 64 bits, matching the
CPUs internal register size). When the Control Unit issues a READ command for a
single address, the memory controller often returns a whole word or even a cache
line, leveraging locality of reference.
The Memory Cycle: This is the sequence of events managed by the Control Unit and
the memory controller to perform a read or write operation. The cycle involves:
Placing the address onto the Address Bus (MAR).
Setting the Read or Write control signal.
Waiting for the memory access time (latency).
Transferring data via the Data Bus (MBR).
2. The Functional Dichotomy: Instructions vs. Data
Memory must store two fundamentally different types of information, both encoded
as binary patterns:
Instructions (Program Code): These are the opcodes and operands dictated by the
Instruction Set Architecture. They are fetched by the Control Unit during the Fetch
phase of the Instruction Cycle and decoded to generate control signals.
Data: These are the operands used by the instructions—variables, constants,
structures, and arrays. They are moved into and out of registers and the ALU during
the Execute and Write-back phases.
In RAM, instructions and data are intermingled in the same address space, but the
Control Unit differentiates them based on the current stage of the Instruction Cycle.
Part III: RAM vs. ROM – The Essential Distinction
The primary memory of a computer system is fundamentally divided based on two
properties: volatility and write capability. This distinction is necessary for system
stability and operation.
1. Random Access Memory (RAM)
RAM is the primary working memory of the computer, providing the fast, temporary
storage necessary for active processing.
Random Access: The defining feature of RAM is that the time required to access any
specific memory location is constant, regardless of its physical location. This is
crucial for performance, as the CPU needs rapid, unpredictable access to any
instruction or data point.
Volatility (The Defining Trait): RAM is volatile. When electrical power is removed or
interrupted, all data stored in the RAM is instantly and irrevocably lost. This is a
direct consequence of the physical storage mechanisms used for speed.
Read/Write Capability: RAM is designed for high-speed, frequent reading and
writing. The CPU constantly writes new data (results of calculations, updated
variable values) and reads both instructions and operands from RAM.
Purpose: RAM hosts the entire execution environment: the kernel of the Operating
System, device drivers, all running application programs, and all data being actively
processed (e.g., your unsaved document). Its speed is paramount.
2. Read-Only Memory (ROM)
ROM is the foundational, static memory of the system, designed for permanence and
stability.
Non-Volatility (The Defining Trait): ROM is non-volatile. The data stored in ROM
persists indefinitely, even when power is completely removed. This property is
achieved through physical or electrical changes in the memory cell structure, not
volatile charge storage.
Read-Centric Design: As the name implies, ROM is primarily designed to be read.
While modern ROM variants can be written to, the write operation is typically slow,
infrequent, and requires specialized circuitry.
Purpose: ROM stores essential, immutable system software that must be available
the moment the computer is powered on. This includes the BIOS (Basic
Input/Output System) or UEFI (Unified Extensible Firmware Interface), which
contains the boot-up instructions (Power-On Self-Test or POST) and the code
necessary to initialize the hardware and load the operating system from the
secondary storage. ROM provides the initial sequence of instructions that
bootstraps the entire computational process.
Part IV: A Deeper Dive into RAM Technologies
RAM is not a monolithic concept; it is implemented using different technologies,
each optimizing for either speed or density/cost. The two main types are Static RAM
(SRAM) and Dynamic RAM (DRAM).
1. Static Random Access Memory (SRAM)
SRAM is the fastest and most expensive type of primary memory, used where
absolute speed is required, primarily within the CPU itself.
The Storage Cell: An SRAM cell consists of a six-transistor circuit (typically four
transistors forming a latch, and two access transistors). This configuration forms a
flip-flop—a bi-stable circuit that can hold one of two states (0 or 1) indefinitely, as
long as power is supplied.
Speed and Access: SRAM is extremely fast because it requires no external effort to
maintain the data once written. It offers the fastest access times, often measured in
nanoseconds or less, perfectly matching the speed requirements of the CPU clock.
The Cost of Speed:
Low Density: Each cell requires six transistors, making the SRAM cell physically
large. This means less storage capacity can fit onto a single chip, increasing cost.
High Power Consumption: The continuous current flowing through the transistors
of the latch, even when idle, leads to higher power consumption.
Usage: SRAM’s expense and speed dictate its use for the CPU’s Cache Memory (L1,
L2, L3). Caches are small, dedicated blocks of fast memory that sit hierarchically
between the CPU registers and the main DRAM, holding the most frequently used
instructions and data.
2. Dynamic Random Access Memory (DRAM)
DRAM is the dominant form of main memory in almost all computers today,
prioritizing density and cost efficiency over absolute speed.
The Storage Cell: A DRAM cell consists of a single transistor and a single capacitor
(1T/1C). The capacitor stores the electrical charge: a charged capacitor represents a
, and a discharged capacitor represents a . The transistor acts as a switch to control
access to the capacitor.
The Volatility Mechanism (Dynamic Refresh): The charge stored in the capacitor is
prone to leakage over time, meaning the data will decay. To prevent loss, the data in
DRAM must be read and rewritten (refreshed) thousands of times per second
(hence "Dynamic"). This continuous refresh cycle is managed by a dedicated DRAM
Controller.
Speed and Density:
High Density: The 1T/1C structure makes the cell physically tiny, allowing billions of
cells to be packed onto a single chip, resulting in very low cost per gigabyte.
Slower Access: The need for refresh cycles and the complex process of reading the
minute charge from the capacitor (which involves destructive reading that requires
immediate rewriting) makes DRAM inherently slower and subject to higher latency
than SRAM.
Usage: DRAM forms the bulk of the main system memory (the RAM sticks you install
in a computer), offering a large, cost-effective workspace for the OS and
applications. Modern variants like DDR SDRAM (Double Data Rate Synchronous
DRAM) use sophisticated techniques to improve throughput.
Part V: A Deeper Dive into ROM Technologies – The Evolution of Persistence
The concept of ROM has evolved significantly, moving from factory-set, truly read-
only chips to electrically alterable, non-volatile storage that forms the basis of
modern secondary memory (like SSDs).
1. Mask ROM (MROM)
Mechanism: The earliest form of ROM, where data is physically etched into the
silicon during the manufacturing process. The presence or absence of a transistor
connection at an address is what defines the stored bit.
Characteristics: Extremely high density, low cost (in high volume), and truly read-
only. Cannot be changed after manufacturing. Used only for the most basic, stable
firmware.
2. Programmable Read-Only Memory (PROM)
Mechanism: Shipped blank with a fuse or link at every bit location. A bit is
programmed to by applying a high voltage pulse to blow the fuse, creating a
permanent break.
Characteristics: Field-programmable (can be written once by the user, not the
manufacturer). One-time programmable (OTP). Once a fuse is blown, it cannot be
reversed.
3. Erasable Programmable Read-Only Memory (EPROM)
Mechanism: Stores data as a charge trapped on a floating gate transistor. The
programming process uses high voltage to force charge onto the gate. The charge is
retained for years.
Erasure: The charge can be removed by exposing the chip to intense ultraviolet (UV)
light for 10-20 minutes, which makes the chip transparent and visible to the user.
This is an inconvenient, non-electrical process.
4. Electrically Erasable Programmable Read-Only Memory (EEPROM)
Mechanism: Similar to EPROM, but uses Fowler-Nordheim tunneling (a quantum
mechanical effect) to electrically remove the charge from the floating gates, bit by
bit.
Characteristics: Can be programmed and erased electrically, without removing the
chip from the system. However, the erasure process is typically slow and can only be
performed on a limited number of times (endurance).
5. Flash Memory (The Modern ROM Successor)
Flash memory is the dominant form of non-volatile storage today, combining the
electrical erasability of EEPROM with much higher density and lower cost.
Mechanism: Based on floating-gate transistors, but allows for bulk erasure in large
blocks (hence "flash" erasure, as opposed to bit-by-bit erasure).
Types and Usage:
NOR Flash: Allows random access for reading, making it ideal for storing firmware
(like the BIOS/UEFI on a motherboard) because instructions can be executed
directly from the chip.
NAND Flash: Offers higher density and faster write speeds (when writing a block),
but only allows sequential reading within a page. This is the technology used in
almost all Solid State Drives (SSDs), USB drives, and memory cards. It requires a
complex Flash Translation Layer (FTL) to manage wear-leveling and present a
conventional block-addressable disk interface to the Operating System.
Part VI: The Memory Hierarchy – The Necessity of Layering
The distinction between the various types of memory only makes sense when
viewed within the context of the Memory Hierarchy. The CPU designer is forced to
make a continuous trade-off between three conflicting properties: Speed, Size, and
Cost.
1. The Trade-Off Principle
Fast memory is expensive and small. (SRAM)
Slow memory is cheap and large. (DRAM, Disk)
The hierarchy is structured to exploit the principle of locality of reference—the
tendency of a program to reuse data and instructions that have been recently
accessed (temporal locality) or that are located near recently accessed data (spatial
locality).
2. The Hierarchy Layers (From CPU Outward)
CPU Registers: Fastest (single clock cycle access). Smallest (tens of words). Volatile.
L1 Cache (SRAM): Extremely fast (2-4 clock cycles). Small (tens of kilobytes).
Volatile. Managed entirely by the Control Unit.
L2/L3 Cache (SRAM): Very fast (10-40 clock cycles). Larger (megabytes). Volatile.
Main Memory (DRAM): Slower (hundreds of clock cycles or more). Large
(gigabytes). Volatile. The OS and all applications reside here.
Secondary Storage (NAND Flash/SSD): Slowest for random access. Very large
(terabytes). Non-volatile (The modern form of data persistence).
The Control Unit and the Memory Management Unit (MMU) constantly manage the
flow of data up and down this hierarchy, striving to ensure that the CPU almost
always finds the data it needs in the fastest, highest layers (the Caches).
Part VII: The CU-Memory Interaction – Timing and Latency
The performance of the entire system hinges on the Control Unit’s ability to
communicate efficiently with the Main Memory (DRAM). Memory speed is not
defined by simple access time but by complex timing parameters.
1. Latency and Throughput
Latency: The delay between the CU issuing a READ command and the data arriving
back at the CPU. This is the key performance bottleneck. Due to the physical
distance and the slow, dynamic nature of DRAM cells, memory latency is high
(hundreds of clock cycles).
Throughput: The rate at which data can be transferred once the connection is
established (e.g., Gigabytes per second). Modern DRAM focuses heavily on
improving throughput via techniques like burst mode transfer and multiple data
channels (the "Double Data Rate" in DDR).
2. The DRAM Access Protocol (Managed by the CU)
The CU does not simply read a single byte; it interacts with the DRAM controller
using a precise sequence to activate the row and column addresses:
Row Address Strobe (RAS): The CU sends the Row Address, which activates an
entire physical row of memory cells.
Column Address Strobe (CAS): The CU then sends the Column Address, selecting the
specific data word within the activated row.
Timing Parameters: The Control Unit must adhere to strict timing parameters (e.g.,
RAS-to-CAS delay, precharge time) defined by the JEDEC standards. The CPU’s
internal timing generator must precisely match these external memory
requirements, inserting wait states if necessary to accommodate the slower
memory subsystem. This tight synchronization is one of the most demanding tasks
for the Control Unit.
Part VIII: Virtual Memory – The Illusion of Infinite RAM
The Control Unit’s interaction with memory is complicated by the concept of Virtual
Memory, which creates an abstraction layer managed by the Operating System,
providing the illusion that each application has access to its own large, contiguous
block of RAM, even if the total physical RAM is smaller.
1. The Role of the Memory Management Unit (MMU)
The MMU is a dedicated piece of hardware (often integrated into the CPU) that
translates virtual addresses generated by the CPU’s instructions into physical
addresses in DRAM. The MMU is entirely controlled by the operating system
through special control registers defined in the Instruction Set Architecture.
Address Translation: When the CPU (under direction of the CU) generates a virtual
address, the MMU uses a special data structure called the Page Table (stored in
RAM) to look up the corresponding physical address. The MMU then directs the
memory access to the correct physical location.
Translation Lookaside Buffer (TLB): To prevent having to read the Page Table from
slow DRAM for every memory access, the MMU uses a small, very fast SRAM-based
cache called the TLB to store recently used address translations. This is another
crucial layer in the memory hierarchy.
2. Paging and Non-Volatile Secondary Storage
Virtual memory relies heavily on the cooperation between volatile RAM and non-
volatile secondary storage (Disk/SSD).
Page Faults: If a virtual address requested by an instruction is not currently mapped
to a physical address in RAM (because the data/code page has been temporarily
moved to the non-volatile disk), the MMU triggers an internal CPU exception called a
Page Fault.
CU Response: The Control Unit immediately saves the program state and jumps to
the operating system’s page fault handler. The OS then:
Locates the required page on the non-volatile disk (secondary storage).
Reads the data from the disk back into a free physical frame in the volatile DRAM.
Updates the Page Table and TLB.
The CU then resumes the original program execution, transparently to the
application.
This process demonstrates how the volatile (RAM) and non-volatile (disk)
memories work together, managed by the Control Unit, to create a stable, vast, and
secure execution environment.
Part IX: Conclusion – The Memory Dichotomy
The concept of memory, segmented into RAM and ROM, is far more complex than
simple storage. It is the defining architectural trade-off that shapes system
performance, cost, and stability.
The speed-cost tension forces the creation of the elaborate memory hierarchy
(registers, SRAM caches, DRAM main memory, and non-volatile flash storage), with
the Control Unit acting as the dynamic traffic cop, enforcing the rules of locality to
maximize the effective speed of the entire storage subsystem. The distinction
between RAMs volatility and ROMs non-volatility is not negotiable: volatile RAM
provides the necessary speed for computation, while non-volatile ROM and its
descendants provide the necessary persistence for the systems foundational
identity and long-term data storage.
A deep understanding of the physical implementations—the 6T cell of SRAM versus
the 1T/1C cell of DRAM, and the evolution of ROM from physical masks to
electrically erasable flash memory—reveals the engineering genius required to
balance the requirements of speed, capacity, and permanence. The entire execution
of the Instruction Set Architecture hinges on the Control Units flawless, synchronous
interaction with this highly layered and diversified storage substrate.
