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HOMEWORK 4: ESSENTIAL TERMS AND CONCEPTS
CSE 230 - Computer Organization and Assembly Language Programming
ASU Temple Campus
Homework
October 14, 2020
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ESSENTIAL TERMS AND CONCEPTS
1. What is the function of a CPU?
Central Processing Unit (CPU) refers to the most important part of a computer that
processes instructions and is also the one that determines how the whole system works. It
does simple arithmetic, logic, control and input/output operations based on program
requirements. Basically, the CPU retrieves instructions in memory, de-codes them to come
up with the necessary action that needs to be taken, and then executes the action itself and
stores the outcome. This cycle helps the CPU to organize and execute all the activities in the
computer system.
3. What does the control unit do?
The control unit (CU) is the unit that is in control and coordination of all the operations in
the CPU. It reads the program instructions brought in memory, and converts them into
particular control signals used to drive the flow of data between the ALU, registers, memory
and the input/output devices. Through sequencing, the CU is also able to make sure that
every part of the processor does its job in the right sequence and at the right time. It does not
manipulate data itself, rather, it oversees and coordinates the performance of commands, and
it acts as the brain of the operations of the CPU.
5. How does the ALU know which function to perform?
The Arithmetic Logic Unit (ALU) determines which operation to perform through
control signals generated by the control unit. When an instruction is decoded, the control unit
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identifies the operation code (opcode) and sends the corresponding control signals to the
ALU. These signals activate specific circuits within the ALU responsible for arithmetic
operations (like addition or subtraction) or logical operations (like AND, OR, or NOT). This
process ensures that the ALU executes exactly the operation required by the current
instruction.
7. What is the difference between a point-to-point bus and a multipoint bus?
A point-to-point bus is used to interface only two components, including a CPU and a
memory module, and to provide a special communication channel. This installation will
enable quicker data communication and minimize interference since no other devices will
share the connection. Conversely, a multipoint bus (also known as shared bus) is one in
which a bus is attached to several components. Although this causes it to be more flexible
and cost-effective in interconnection of many devices, it may cause data collisions, and bus
arbitration is necessary to control access. In fact, point-to-point buses are fast and easy to use,
whereas multipoint buses can be expanded and also share communications.
9. Explain the differences between data buses, address buses, and control buses.
An actual data transfer between components e.g., between the CPU and memory and
between the CPU and the I/O devices occurs in a data bus. The address bus contains the
memory addresses of the place of data to be accessed or read; it is used to know the origin of
data or where data is to be stored. Control signals are transmitted on a control bus and control
and coordinate the system activity, including read/write commands, interrupt signals, and
clock signals. Simply put, the information is moved with the data bus, the destination is
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defined with the address bus, and the methods and timing of the transfer is determined with
the control bus.
11. Name three different types of buses and where you would find them.
The primary communication channel is the system bus that links the CPU, the main
memory and other important units like I/O controllers. It is conventionally broken into data,
address and control lines that combine in order to convey information in the system. System
bus is also important because it is the foundation of communication between the processor
and memory that determines the overall speed and performance of the computer.
The internal bus is fully enclosed within the CPU and connects the internal parts of the
CPU like the Arithmetic Logic Unit (ALU), the control unit, and the registers. This is
because this bus means that data transfer and processing can be done fast within the
processor without necessarily involving the use of external pathways. The design has a direct
influence on the efficiency of the CPU to perform instructions, and it is necessary to support
rapid internal operations.
The external bus links the main system and the CPU with the external peripheral devices
that are not part of the core architecture, including printers, external storage as well as other
I/O devices. It enables data transfers in between the computer and externals such as
standardized interfaces such as USB, PCIe or SATA. In contrast to the internal and system
buses, the external one needs to be able to operate with a very large variety of types and
speeds of devices and compatibility and protocol management are particularly significant in
this case.
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13. What are the four types of bus arbitration?
The daisy chain arbitration scheme, interlocks devices in a sequence, in which the
precedence is established by the location of the device on the bus. The device nearer to the
controller of the bus is given priority and the arbitration signal is sent out along the chain
until it reaches a device that requires access. It is an easy and low-cost method but may cause
lower-priority devices to starve in case higher-priority devices consume the bus often.
The centralized parallel arbitration approach consists of a single bus controller that takes
requests to all the devices. Every device has its request and grant lines and the controller
decides which device to allow to access the bus based on a specified priority scheme. This
approach is quicker than daisy chaining as all the devices may request access simultaneously,
though it needs additional hardware lines and a more detailed controller.
The distributed arbitration by self-selection process ensures that the different devices
determine their own priority by marking a different code on common arbitration lines. Every
device evaluates their codes at the same time and the one with the highest priority is awarded
ownership of the bus. As there is no one central controller, this approach removes a single
point of failure and enables arbitration to be faster. It however needs more advanced logic in
any given device.
The distributed arbitration by collision detection mechanism, which works in a manner
similar to the way Ethernet works, does allow several devices to seek to use the bus
simultaneously. In case of collision, the devices identify it and repeat it with a specific
algorithm which is defined like random backoff. This is very dynamic and it allows fluid
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priorities but will cause delays during periods of heavy traffic as it will cause repeated
collisions.
15. How do system clocks and bus clocks differ?
The difference between system clocks and bus clocks is that they play different roles and
have various speeds of operation in the computer. The system clock is used to time the CPU
and other core components which determines the speed at which the processor runs
instructions. It is usually very fast running in order to facilitate speedy processing. The bus
clock on the other hand dictates when data has to be transferred between the CPU, memory
and peripheral devices over the system bus. Bus clocks typically have a reduced frequency
than system clocks to fit the ability of linked devices and minimize signal integrity problems
over a longer distance. This separation enables the CPU to operate with high speeds without
compromising the communication with other components.
17. Explain the difference between memory-mapped I/O and instruction-based I/O.
Memory-mapped I/O The control registers of I/O devices are treated like normal system-
main memory. It implies that the instructions required to access memory (such as load and
store) are also utilized to communicate with I/O devices. It makes the instruction set simpler
and enables the CPU to perform the same addressing modes and operation on both memory
and I/O to be more flexible. Nevertheless, it decreases the address space that can be used by
the regular memory as some of the addresses are occupied by I/O.
Instructions-based I/O or isolated I/O makes use of an independent set of instructions
with the purpose of communicating with I/O devices (e.g. IN and OUT instructions). This
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technique maintains separate I/O and memory address spaces, and therefore does not
sacrifice the entire memory address range of data and programs. But it needs extra
instructions in the CPU instruction set, and control logic separate to the I/O operations.
19. Explain the difference between byte addressable and word addressable.
A unique address in memory in a system based on a byte addressable system refers to one
singlebyte. This enables the processor to access single bytes directly thus flexible in
processing data of different sizes, including characters or small types of data. The majority of
computer systems in modern times incorporate the use of byte addressing since it is
compatible with common programs and data models.
In a word-addressable system, every memory address refers to a word which typically
consists of a fixed number of bytes (2, 4 or 8). Operation of single-byte access can be even
more expanded since the system operates at a word level. Although it can make hardware
design simpler and can enhance performance in certain applications, it becomes less
adaptable to applications that need to work with single-byte data very often.
21. List and explain the two types of memory interleaving and the differences between
them.
The two primary interleaving memories include high-order interleaving and low-order
interleaving and the difference between them is in the distribution of memory addresses to
memory modules.
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In the high-order interleaving, the bits of the address that are at the higher order select the
memory module to access. This implies that successive groups of addresses are located in
one module and then transferred to the next one. High-order interleaving is employed when
the extent of data that requires storage by the same module is large and contiguous, but may
cause a performance bottleneck in the case that multiple consecutive addresses are visited at
the same moment, as they all can point to the same module.
In low-order interleaving, the bits of the address that are of the low order choose the
memory module and the consecutive memory addresses are shared among several memory
modules in a round-robin manner. This enables the CPU to have access to several modules of
the memory at the same time, enhancing the memory bandwidth and performance. Low-order
interleaving is particularly useful in the systems where sequential instructions or data is
accessed frequently since it minimizes the wait by overlapping memory operations.
The main distinction between high- and low-order interleaving groups is that high-order
interleaving groups sequential addresses within a single module, whereas low-order
interleaving sequential addresses across a variety of modules to permit parallel access and
improved performance in most contemporary architectures.
23. How does a maskable interrupt differ from a nonmaskable interrupt?
An interrupt that may be ignored or masked by the status register of the CPU is known as
a maskable interrupt. This enables the processor to temporarily disable some of its interrupts
as it exploits the processor resources in performing important functions so that interrupts that
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are less important or urgent do not interrupt the current tasks. Routine I/O or other noncritical
events will normally use maskable interrupts.
An NMI, conversely, is one that cannot be suppressed by the CPU. It is to be used in high
priority or emergency cases, including failure of hardware or critical system notifications, in
which case immediate response is needed. Since the CPU is unable to disregard NMIs, they
make sure that important matters are dealt with immediately.
25. Explain the functions of all of MARIE’s registers.
MARIE has quite a number of important registers, and each one of them is used in a
certain part of the fetch-decode-Execute cycle and overall processing of instructions.
The Accumulator (AC) contains information temporarily in the process of arithmetic and
logic operation. It is the main register that is used in calculations in which intermediate
results and final outputs are stored.
Memory Buffer Register (MBR) is a temporary storage of data that is in transit to or out
of memory. When the CPU reads some contents in the memory the contents are initially
stored in the MBR and then transferred to another register. In the same fashion, data is
transferred to memory when one writes to memory.
The Memory Address Register (MAR) contains the address of the next location of the
memory that is to be accessed by the CPU. It helps in ensuring that the right memory location
is chosen when doing the read and write operations.
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Instructions currently being executed are stored in the Instruction Register (IR). Once an
instruction has been retrieved in memory it is stored in the IR so it can be decoded and run by
the control unit.
The Program Counter (PC) maintains the address of the next instruction that is to be
fetched. The PC is automatically updated after a fetch to allow the CPU to know the next
instruction location.
Lastly, there are the Input Register (InREG) and the Output Register (OutREG) which is
used to perform input and output functions. InREG contains data to be inputted and OutREG
contains data to be outputted. These registers combined enable MARIE to carry out I/O
operations without immersing in the issues.
27. Explain how each instruction in MARIE works.
The MARIE set of instructions is built on a simple load-store architecture with the
instructions each performing a particular task during the fetch-decode-exec cycle. It is
comprised of logic of data transfer, arithmetic, input/output processing and control. Load X
(data movement instructions) load the value of the memory address X and store it in the
Accumulator (AC) by setting the MAR to X, loading the value of Location X in the MBR
and transferring it to the AC. Store X on the other hand stores the contents of the AC to
memory address X by telling the AC contents to the MBR and recording it to the memory.
Arithmetic operations consist of operations such as Add X, which retrieves the value at
address X, and adds it to the AC, and Subt X, which subtracts the value in memory to the AC
and so on.
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External communication is done in input/output instructions. Input instruction converts
the contents of input register (InREG) into the AC and the Output instruction transfers the
contents of the AC to the output register (OutREG), which may be then displayed or sent to
an external device. Halt instruction halts the execution of a program.
Decision-making and sequencing are made possible with control flow instructions. Jump
X changes the normal course of execution by setting the address X to the Program Counter
(PC) which causes the following instruction fetch to be that address. Skipcond assesses
certain qualifications in the AC, like, did its value become negative, zero, or positive, and,
should the qualification be satisfied, it adds one to the PC to skip the next instruction. Clear
also sets the AC to the zero. Combined, these instructions enable MARIE to execute the
necessary computational operations, which is how the fundamental roles of a basic stored-
program computer are revealed.
29. What is the significance of RTN?
Register Transfer Notation (RTN) is important since it enables a description at the
hardware level, with great accuracy of the flow of data among registers and other
components during the execution of instructions. RTN is a representation of operations in a
step-by-step, highly symbolic, manner that resembles representations of what occurs within
the CPU. It can be quite handy in the depiction of the fetch-decode-execute cycle, that is, the
division of instructions into microoperations, i.e. loading the registers, transferring data, or
executing ALU operations. With RTN, the designers and students do not need to rely on
extensive verbal explanations about the inner process of each instruction to clearly
understand it and document it.
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31. How does a microoperation differ from a regular assembly language instruction?
A microoperation is a low-level operation operating inside the internal components of the
CPU such as the movement of data between registers or a single calculation of the ALU.
Microoperations can be found in every cycle of the instruction and are not visible to the
programmer.
By comparison, an ordinary assembly language instruction is a higher-level command
that the programmer has written, e.g. LOAD or ADD. The assembly instructions are usually
divided into several microoperations as they are being executed. That is, microoperations are
the most basic operations which execute the behavior of assembly instructions.
33. How does interrupt-driven I/O work?
The interrupt-driven I/O enables the CPU to execute other functions as I/O operations are
pending to enhance efficiency of the system. An I/O device interrupts the CPU when it
completes its work or needs to be attended to. The CPU puts its current execution on
temporary hold, stores the state of the program, and gives control to an interrupt service
routine (ISR) that is intended to take care of the request of the device. Once the interrupt has
been serviced, the CPU transfers the prior state and resumes the interrupted program. This
helps to avoid the issue of constant CPU polling and thus save the time that would be wasted
on processing, enabling the processor to attend to other activities until an I/O device indicates
it is complete.
35. What is an embedded system? How does it differ from a regular computer?
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An embedded system is a specialized computing system designed to perform dedicated
functionality and is typically a component of a larger device. Embedded systems are
designed to perform particular functions efficiently and reliably, with respect to general-
purpose computers, which can perform most types of applications. Examples of devices
found in these instances include household appliances, cars, medical equipment, and
industrial machines.
Embedded systems differ significantly from ordinary computers. Their hardware
resources are typically less (smaller memory and processing power) since they are
specialized in their applications and not in general usefulness. They are also typically used in
real-time operating environments, where timely operations are required to take place within
strict timeframes. Moreover, end users do not normally reprogram embedded systems, unlike
regular computers, which are programmable and can install and execute many software
programs.
37. Explain the difference between hardwired control and microprogrammed control.
Hardwired control employs fixed electronic circuits to directly derive control signals
from the instruction’s opcode and timing signals. The control unit is designed with
combinational logic, i.e., the control signals of each instruction are explicitly routed through
predefined wiring paths. As a result, the execution is faster since there is no need for
additional control instruction fetch or interpretation. Nevertheless, it is less flexible; a change
in the instruction set necessitates a hardware redesign, thus, it is more complicated to update
or extend.
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Whereas microprogrammed control utilizes a small, dedicated memory (the control store)
containing microinstructions. These microinstructions are fetched in a sequence to produce
the required control signals for the given machine instruction. This method is more adaptable
and less problematic to modify since changes in the instruction set or control behavior can be
effected by simply updating the microprogram instead of changing the hardware. However, it
may be slower than hardwired control because of the additional steps of fetching and
decoding microinstructions.
Essentially, hardwired control gives up flexibility for speed and ease of implementation
with a fixed instruction set, whereas microprogrammed control provides flexibility and easier
upgrades but slower execution.
39. Compare CISC machines to RISC machines.
CISC (Complex Instruction Set Computer) systems are equipped with a large and
complicated set of instructions, where some instructions may perform multiple low-level
operations within a single instruction. The intention of this design is to minimize the number
of instructions per program, thus making assembly programming more user-friendly and
possibly lowering memory usage. But due to the fact that the instructions are complex and of
varying lengths, CISC architectures cannot be executed within a single clock cycle and
therefore multiple clock cycles are needed to carry out one instruction; also, CISC
architectures require more complex control units, which often utilize microprogrammed
control.
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On the other hand, RISC (Reduced Instruction Set Computer) systems utilize a smaller
and simpler set of instructions, where each instruction is aimed at very quick execution—
generally in a single clock cycle. RISC architectures focus on factors such as simplicity,
speed, and efficient pipelining, which enable the processing of multiple instructions
simultaneously. Thus, even though there may be more instructions per program in
comparison with CISC, the total execution time is, in many cases, shorter because each
instruction has a uniform structure and is highly optimized. Typically, RISC utilizes
hardwired control for rapid and stable performance.
41. Name four Intel processors and four MIPS processors
The development of computing technology has over the years been marked by four
remarkable examples of Intel processors. Intel 8086 is one of the first 16-bit processors and
the predecessor of the modern x86 architecture which continues to dominate the personal
computers today. This was followed by the Intel Pentium, which became popular in the
1990s, which introduced the concept of a superscalar architecture, that is, multiple
instructions can be executed in parallel and created a new benchmark in consumer
performance. The Intel core i7 family has emerged as a high-performance processor line that
is widely used in desktops and laptops in the modern world since it offers balance in speed,
efficiency and multitasking. Servers and workstations have the Intel Xeon series which is
developed specifically to be used in a demanding environment supported by high reliability,
larger cache memory and multiprocessing capabilities to achieve an enterprise level
workload.
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On the same note, the MIPS architecture has a number of powerful processors. R2000
was the first 32-bit MIPS processor, and one of the first processors to use the traditional
RISC (Reduced Instruction Set Computing) design philosophy, emphasizing efficiency and
simplicity. Its successor, R3000, was more successful and introduced support of
multiprocessors making it work with more sophisticated system. A significant breakthrough
was the R4000, as it was among the first commercially available 64 bit processors and this
greatly enhanced the capabilities of MIPS. Lastly, the R10000 was an implementation of a
high-performance superscalar that had become embedded in powerful workstations and
servers, making MIPS a legitimate force in high-end computing.
PART 2 E4, E6, E8, E10, E12 AND E14
4. How many bits would you need to address a 2M × 32 memory if:
a) Byte Addressable
If the memory is byte addressable, then each byte has a unique address. Given that the memory is
2M × 32, there are 2 million words, and each word consists of 32 bits, which equals 4 bytes. The
total number of bytes can be calculated as:
Total bytes = Number of words × Bytes per word
= 2M × 4
= 2 × 2²⁰ × 4
= 2²¹ × 2²
= 2²³ bytes.
To address 2²³ unique byte locations, we need 23 address bits.
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b) Word Addressable
If the memory is word addressable, each word has a unique address. The total number of words
in memory is 2M, which equals 2 × 2²⁰ = 2²¹ words. To uniquely address each of these 2²¹ words,
we need 21 address bits.
Answer
a) 23 bits (byte addressable)
b) 21 bits (word addressable)
6. How many bits are required to address a 1M × 8 main memory if:
a) Byte Addressable
For a 1M × 8 main memory, each word is 8 bits, which equals 1 byte. If the memory is byte
addressable, each byte has its own unique address. The total number of bytes in memory is
therefore 1M (1 × 2²⁰). To address 2²⁰ unique byte locations, we need 20 address bits.
b) Word Addressable
If the memory is word addressable, each word has its own address. Since each word is 1 byte, the
total number of words is also 1M (2²⁰). Therefore, we still need 20 address bits to uniquely
address each word.
Answer
a) 20 bits (byte addressable)
b) 20 bits (word addressable)
8. Suppose we have four memory modules instead of eight in Figures 4.6 and 4.7. Draw the
memory modules with the addresses they contain using:
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ANSWERS:
Interleaving distributes consecutive addresses across multiple memory modules to improve
parallelism and bandwidth. With 4 modules, two select bits are needed (since 4 = 2²). Below we
illustrate mappings using a small example address range (0 through 15) to make the pattern clear.
For a larger address space, the same rules apply: high-order uses the most significant module-
select bits, low-order uses the least significant module-select bits.
Assumptions for the illustration
1. We illustrate addresses 0 through 15 (16 addresses) as an example.
2. With 4 modules, 2 bits are required to select a module (00, 01, 10, 11).
3. For the example we show which addresses each module contains under both schemes.
4. LSB = least-significant bit, MSB = most-significant bit.
a) High-order interleaving
Rule: The high-order bits of the address determine the module. Consecutive address blocks are
placed entirely in the same module.
For addresses 0..15 (4 modules), split the 4-bit address as [module-select (2 bits)] [offset (2
bits)]. Module-select = high-order 2 bits.
Mapping (contiguous blocks):
Module 0 (module-select = 00): addresses 0 → 3 (binary 0000–0011)
Module 1 (module-select = 01): addresses 4 → 7 (binary 0100–0111)
Module 2 (module-select = 10): addresses 8 →11 (binary 1000–1011)
Module 3 (module-select = 11): addresses 12 →15 (binary 1100–1111)
1. Visualization (each row is a module):
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Module 0: [0, 1, 2, 3]
Module 1: [4, 5, 6, 7]
Module 2: [8, 9, 10, 11]
Module 3: [12, 13, 14, 15]
b) Low-order interleaving
Rule: The low-order bits of the address determine the module. Consecutive addresses are spread
across modules in a round-robin fashion, improving parallel access to sequential addresses.
For addresses 0..15, split the 4-bit address as [high-order addr bits for bank offset] [module-
select (2 bits)]. Module-select = low-order 2 bits.
Mapping (round-robin):
Module 0 (module-select = 00): addresses 0, 4, 8, 12
Module 1 (module-select = 01): addresses 1, 5, 9, 13
Module 2 (module-select = 10): addresses 2, 6, 10, 14
Module 3 (module-select = 11): addresses 3, 7, 11, 15
2. Visualization (each row is a module):
Module 0: [0, 4, 8, 12]
Module 1: [1, 5, 9, 13]
Module 2: [2, 6, 10, 14]
Module 3: [3, 7, 11, 15]
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Discussion and generalization
High and low order interleaving are memory addressing strategies that are applied to
accesses among several memory modules. In high-order interleaving, memory addresses of
successive modules are allocated to the same module, and this is advantageous when using large
contiguous blocks of data, but could limit parallelism in the case of sequential access operations.
Low-order interleaving, in contrast, separates one address of each module with another, enabling
access in parallel and the fullest possible parallelism- particularly in instruction fetching and
block transfers. Given an address width of N bits and with memory modules (number M) being
selected by the k bits of the address, the number of bits used in selecting the memory module is
the key to the type of interleaving, where the most significant bits are used to select a module
(high-order interleaving), and the least significant bits are used to select a module (low-order
interleaving).
10. Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that
memory is word addressable.
a) Number of RAM Chips
Total memory capacity = 2M × 16 bits = 2²¹ words × 16 bits = 2²⁵ bits.
Each RAM chip = 256K × 8 bits = 2¹⁸ × 8 = 2²¹ bits.
Number of chips needed = 2²⁵ ÷ 2²¹ = 2⁴ = 16 chips.
b) Chips Involved per Word
Each chip is 8 bits wide, but each word is 16 bits wide.
Therefore, 2 chips must be accessed simultaneously to retrieve or store one word.
c) Address Bits per Chip
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Each RAM chip has 256K locations = 2¹⁸.
Therefore, 18 address bits are required for each chip.
d) Number of Banks
A bank is a set of chips that operate together to provide the word size.
Each bank = 2 chips (to provide 16 bits).
Number of banks = Total chips ÷ Chips per bank = 16 ÷ 2 = 8 banks.
e) Address Bits for All Memory
The memory is word addressable and has 2²¹ words.
Therefore, 21 address bits are required to address the entire memory.
f) High-order Interleaving (Address 14 / 0xE)
With 8 banks, 3 bank-select bits are required.
In high-order interleaving, the most significant address bits select the bank.
Address 14 (0xE) in binary: 000...01110. The high 3 bits are 000, selecting Bank 0.
Offset within the bank = 14.
Address 0xE is located in Bank 0 (the two chips of that bank).
g) Low-order Interleaving (Address 14/0xE)
In low-order interleaving, the least significant 3 bits select the bank.
Address 0xE = binary ...00001110. The low 3 bits are 110 (decimal 6).
Address 0xE is located in Bank 6 (the two chips of that bank).
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12. Suppose we have 1G × 16 RAM chips that make up a 32G × 64 memory that uses high
interleaving. (Note: This means that each word is 64 bits in size and there are 32G of these
words.)
Given and interpretation
Each RAM chip has a capacity of 1G × 16, meaning it holds 1 gigaword (where 1G =
2³⁰) with each word being 16 bits wide. The overall system memory is specified as 32G × 64,
giving a total of 32 gigawords (where 32G = 2³⁵), with each word consisting of 64 bits. For
calculations and configuration in parts a through e, high-order interleaving is assumed, while
part f specifically switches to low-order interleaving. Additionally, when comparing the sizes
of the RAM chips to the overall system capacity, all measurements are treated in terms of total
bits to maintain consistency across calculations.
. a) Number of RAM chips
Capacity per chip (bits) = 2³0 words × 16 bits/word = 2³0 × 2⁴ = 2³4 bits.
Total system capacity (bits) = 2³5 words × 64 bits/word = 2³5 × 2⁶ = 2⁴1 bits.
Number of chips = 2⁴1 ÷ 2³4 = 2⁷ = 128 chips.
Answer (a): 128 RAM chips.
b) Number of banks (4 chips per bank)
Each bank is formed by 4 chips operating in parallel to produce the 64-bit system word (4 × 16 =
64).
Number of banks = total chips ÷ chips per bank = 128 ÷ 4 = 32 banks.
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Answer (b): 32 banks.
c) Lines to each chip
A memory chip has address lines, data lines and a small number of necessary control
lines to be operational. Given that 230 words can be stored in a single chip, it means that it has to
be connected to 30 address lines to get access to every memory location in a unique way.
Moreover, due to the width of chips, that is 16 bits, it requires 16 data lines to transmit and
receive data. In addition to these, it requires few control lines, which generally have Chip Select
(CS), Output Enable (OE) and Write Enable (WE) to control read and write operations. All these
connections allow appropriate communication between the memory chip and the processor.
Answer (c): 30 address lines and 16 data lines per chip (plus CS/OE/WE).
d) Address bits for entire memory (word-addressable)
Total words in system = 32G = 2³5 words. Therefore, number of address bits = 35.
Answer (d): 35 address bits.
e) Bit decomposition (High-order interleaving)
The 35-bit system address must be divided into two parts: a set of bank-select bits used
to identify one of the 32 memory banks, and a set of on-chip address bits used to access one of
the 2³⁰ words stored within each chip.
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Since there are 32 banks, bank-select bits = log2(32) = 5 bits. On-chip address bits = 30
bits.
High-order interleaving means the MOST SIGNIFICANT bits select the bank.
Bit layout (MSB → LSB):
[ A34 A33 A32 A31 A30] [ A29 ... A0]
← 5 bits (bank select) → ← 30 bits (on-chip address) →
Interpretation: A34.A30 choose one of the 32 banks. When a bank is selected, its 4 chips are
enabled in parallel. A29.A0 are forwarded to each chip as the internal address lines.
Answer (e): 5 high-order bits for bank select; 30 low-order bits for on-chip address.
f) Low-order interleaving (alternative)
In low-order interleaving, the LEAST SIGNIFICANT bits select the bank (round-robin
assignment).
We still need 5 bank-select bits (for 32 banks) and 30 on-chip address bits, but their positions
swap.
Bit layout (MSB → LSB):
[ A34 ... A5 ] [ A4 A3 A2 A1 A0 ]
← 30 bits (on-chip addr) → ← 5 bits (bank select) →
Interpretation: A4..A0 choose the bank (0..31) in a round-robin fashion; A34..A5 index within
the selected chip.
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Answer (f): Low-order interleaving uses 5 LSBs for bank select and 30 MSBs for on-chip
address.
Summary
a) 128 RAM chips
b) 32 banks (4 chips per bank)
c) 30 address lines and 16 data lines per chip (plus control lines)
d) 35 address bits (word-addressable)
e) High-order: [5 MSB bits = bank select] + [30 LSB bits = on-chip address]
f) Low-order: [30 MSB bits = on-chip address] + [5 LSB bits = bank select]
AI Theory & Core Concepts (Learning Types)
Typically, artificial intelligence learning paradigms are divided into three principal
categories: supervised, unsupervised, and reinforcement learning, each of which is distinguished
by the way the system interacts with data and how the objectives are defined. Supervised
learning depends on labeled datasets where every input has a related target output, thus allowing
algorithms to create explicit mappings between features and predicted outcomes. This method is
used in a variety of areas such as medical diagnosis and speech recognition, as it provides
controlled optimization under measurable accuracy metrics (Chatterjee, 2020). On the other
hand, unsupervised learning is a process that does not have predefined outputs; rather, it derives
the hidden structures or the clustering tendencies of the data distributions. Niel and Bastard
(2019) argue that these techniques play a vital role in anomaly detection and in discovering
patterns in high-dimensional data, especially in situations where the cost of annotation is so high
26
that labeling is not feasible. Furthermore, reinforcement learning separates itself even more by
considering the model as an agent that is in an environment, and the only feedback it gets is
through rewards, instead of ground truth labels (Nandy & Biswas, 2017). The agent, instead of
making static output predictions, eventually learns the policies that lead to the highest long-term
rewards through trial-and-error exploration. These three paradigms in unison constitute the
intellectual basis of current AI machines, and gradually, hybrid strategies are being employed
that combine the advantages of these paradigms to realize strong generalization in situations of
ambiguous information.
Supervised learning systems generally use loss functions to measure the difference
between predicted and actual outputs, thus guiding weight changes through a gradient-based
optimization. The epistemological perfection of this model is its quantifiable learning path,
which allows researchers to very accurately verify convergence and feature sensitivity
(Rachmad, 2016). Nevertheless, the need for labeled data in this method exposes its weaknesses,
especially when human annotation biases affect the representation of the ground truth.
Chatterjee, (2020) asserts that biased training sets can unintentionally implant discriminatory
biases in decision pipelines, thus causing model overconfidence in narrow contexts.
Unsupervised methods, on the other hand, are able to uncover hidden distributions beyond
human assumptions but their interpretability in domains where explainability is required by
regulatory frameworks remains a challenge. Mueller et al. (2019) argue that the outcomes of
clustering or dimensionality reduction frequently do not have a causal explanation, thus their
accountability in the high-stakes environment is questionable. Consequently, reinforcement
learning appears as a philosophically dynamic alternative where, agents, implicitly, learn from
consequences, not instructions. However, its random exploration characteristics can, still, result
27
in ethically undesirable behaviors if reward signals are not properly aligned with human values.
Therefore, the tripartite structure of learning paradigms, while providing methodological
diversity, also demands the presence of a critical oversight when applied.
One of the aspects that reinforcement learning (RL) is significant in terms of is its
temporal dependency structure, in which actions not only affect current situations but also
subsequent states. The ability to take sequential decisions allows RL agents to distill dynamic
environments, including robotics, trading systems and autonomous navigation, where decisions
should be foresight-planned and not instance-response (Nandy and Biswas, 2017). In contrast to
supervised learning, which maximizes fixed mappings, the RL agents need to survive uncertain
and delayed feedback, and as such, exploration-exploitation balance is one of the central
theoretical questions. According to Deng et al. (2020), these adaptive autonomies can be more
effective with edge intelligence architecture in that a decentralized system is able to optimize
local strategies, but these same systems transmit reward policies between distributed nodes.
Nevertheless, the fact that RL is probabilistic in nature poses danger in safety as well when
agents learn the unintended shortcuts which maximize rewards technically, but does not adhere
to human expectations of what should be done. Mueller et al. (2019) emphasize the examples of
the manipulation of the reward functions using the loopholes by AI agents, which demonstrate
the necessity of reward engineering on constraints. Therefore, although RL can provide
unmatched versatility to real-world learning, it has to be kept in ethical guardrails to avoid the
emergent misalignment.
The epistemological differences between the philosophical variations of learning
paradigms are more dramatic in terms of intensity of differences around the definitions of
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intelligences. Supervised learning concurs with the empiricist traditions, which postulate that the
knowledge is learned via labeled association formalized by predictive functions (Rachmad,
2016). The unguided learning is close to the rationalist understanding, which assumes that a
structure can be generated independently of any external teaching. However, the reinforcement
learning fills the gap between pragmatism and behaviorism since it considers the intelligence to
be comparable to the intentional adaptation via the consequence other than a symbolistic
reasoning (Chatterjee, 2020). According to Niel and Bastard (2019), using AI applications in
clinical settings is gaining more and more applications combining these two paradigms to
approximate human multifaceted cognition, using supervised signals to produce a diagnosis and
employing unsupervised anomaly detection and personalization based on reinforcement. It is
important to note that pure categories can be operationally in any case, and conceptually
convenient. In reality, AI, when applied in real life, does not always follow specific paradigms
but, instead, it is an integration of these paradigms based on the needs of a situation.
Philosophically, this change points to an orientation toward the past categorical classification and
continuous learning autonomy spectrums. With the future of AI, the difference between types of
learning will take a back seat as the issues of interpretability and ethical appropriateness arise.
Theoretical advancements in AI in the future may require a reconsideration of the
frontiers of the learning paradigms as a whole. Meta-learning also known as learning to learn is
an analogous form of synthesis where models make flexible internal decisions of learning in
response to previous experiences instead of pre-assigned optimization principles (Nandy and
Biswas, 2017). According to Chatterjee (2020), these types of mechanisms might allow self-
configuring systems that are fluidly shifting between supervised, unsupervised, and
reinforcement-based modes based on the uncertainty about the environment. In the meantime,
29
curriculum learning presents the anthropomorphic structure, which sequences the difficulty of
training, giving the models an opportunity to develop gradually as the human mind (Mueller et
al., 2019). This mingling of terms highlights the fact that intelligence does not just happen to be
the result of being exposed to data, but rather a process of organizational learning. In
philosophical terms, Rachmad (2016) argues that AI needs to be considered not just based upon
its output, but also the learning process with respect to its epistemic integrity. This way, instead
of considering the supervised, unsupervised and reinforcement paradigms as fixed archetypes,
modern scholarship considers them as interacting dialects on a larger evolutionary continuum.
The future of AI learning theory might then be in optimizing the transition between entities
rather than optimization of each entity.
AI in Embedded/Hardware Systems
It has been shown that the introduction of artificial intelligence in an embedded system is
a crucial paradigm shift over a more simplistic static computation towards dynamic on-the-
device cognition. In contrast to cloud based AI inference that requires a remote server to run its
workloads, embedded AI allows models to run locally on microcontrollers, GPUs or tensor
processing units which reduce latency and provide continuity of operation in offline applications.
This intersection between edge computing and machine learning is what Deng et al. (2020) term
edge intelligence and states that it enables real-time responsiveness in mission-critical areas like
autonomous vehicles and medical diagnostics. Convololutional neural networks use hardware
accelerators like NVIDIA Jetson modules or Google Coral TPUs that follow the parallel
architecture to support their inference with milliseconds-size execution windows, which involves
efficient matrix multiplication with the help of parallel tensor cores. Nonetheless, hardware
30
based speed presents new optimization challenges on memeory optimization since due to low
RAM storage capacity, the batch size and model depth are limited. As Chatterjee (2020) notes,
pruning and quantization methods cannot be done without in compressing neural architectures
without reducing predictive fidelity. Therefore, AI that can be implemented in a hardware needs
to be co-designed both at the algorithmic and architectural level to ensure that it can perform
within a stringent energy and spatial domain.
Although traditionally GPUs promoted the democratization of AI computation at high
performance, recent developments in neuromorphic and FPGA-based models indicate that yet
more biologically inspired processing models may be utilized. A neuromorphic chip, one
example being the Loihi, is a model that does not use deterministic instruction cycles but
asynchronous events to propagate spikes to simulate neuronal firing behavior (Niel & Bastard,
2019). This leads to ultra-low-power optimization which is more favorable to long-term
autonomy in mobile robotics and wearable. In the meantime, hardware-level reconfigurability
afforded by field-programmable gate arrays (FPGAs) can be exploited by AI developers to
optimize logic blocks to targeted model structures, and is much more efficient than general-
purpose silicon. As stated by Deng et al. (2020), these architectures provide a transitory space
between traditional CPUs and complete ASIC-based applications, as it is flexible enough to
provide execution throughput without a loss in execution speed. Nevertheless, the barrier of
programmability is also substantial, since it requires hardware description experience that
machine learning engineers often do not have. To fill this gap, hybrid toolchains are thus new
and are becoming automated in their translation of what TensorFlow does into a RTL
configuration. The concomitant development of hardware and AI structures indicates that future
31
intelligence will be constrained not by the abilities of the algorithms but by an electronic
incarnation.
The use of Hardware-bound AI is also important in the distributed sensing environment
where bandwidth restricts the capabilities of the environment. Embedded inference as opposed to
sending raw sensor data to centralized servers provides filtering of decision-making at the early
stage when only actionable results are provided at the upstream. According to Deng et al. (2020),
this is referred to as hierarchical intelligence, in which edge devices are preliminary cognitive
agents, only major events are sent to higher-order coordinators. Indicatively, local availability of
soil and thermal measurements with lightweight neural networks in agricultural monitoring
systems enable real-time adjustments of irrigation systems without the need to rely on clouds.
This kind of decentralized freedom minimises network overload and maximises resilience in
periods of network outage. According to Chatterjee (2020), this decentralization in architecture
corresponds to the philosophical principle of cognitive locality, the presence of intelligent action
on the spot instead of the omniscient control. The distributed AI however demands
synchronization protocols to avoid model drift particularly where the individual nodes are only
updating their parameters independently. Federated averaging provides an incomplete answer,
and because of hardware-related number inconsistencies, it is more difficult to achieve consensus
stability. Therefore, hardware integration goes beyond merely the physical integration, but it
requires unifying integration tactics that would guarantee autonomy and unity within dispersed
machines.
The thermal regulation and energy efficiency are the most vital factors in the software in
hardware-based implementation of AI, especially in a limited setting, like wearables, drones, and
32
industrial sensors. On the contrary to the case of data center with active cooling systems,
embedded devices are required to remain stable in terms of operational conditions when the
surrounding environment is passive (not active). Deng et al. (2020) state that trying to run
compute-heavy models can cause thermal throttling, which results in sudden performance drops
that undermine the reliability of inference. In order to overcome this, engineers are using more
dynamic frequency scaling techniques which seek to vary the rate of computation according to
temperature feedback loop. According to Niel and Bastard (2019), thermal-sensitive scheduling
is apparent, based on biological metabolic homeostasis, so resource consumption is controlled
with environmental constraints. Meanwhile, quantized and binary neural networks can be
optimized to as few as 1-bit representations, which yields computational load by many orders of
magnitude, and classification tasks have still acceptable accuracy. According to Chatterjee
(2020), the theoretical beauty of AI has to eventually bow down to the thermodynamic nature of
its physical infrastructure. Therefore, sustainable AI cannot be quantified in solely the novelty of
algorithms but the capacity to act in a uniform manner subject to the constraints of physical
performance in embodied actions.
Performance is not only the key factor of the long-term viability of embedded AI but also
maintainability, especially in regards to over-the-air (OTA) model updates and backward
compatibility. The deployed models in the static firmware architecture are commonly frozen,
causing a slow obsolescence as data distributions change. Deng et al. (2020) also suggest the
adaptive firmware enabling the replacement of neural components without resorting to a
complete system reboot. Nonetheless, this type of architecture must have compatibility layers
that allow old hardware drivers to use new tensor graphics settings. According to Chatterjee
(2020), version fragmentation poses a philosophical dilemma because individual devices at one
33
time or another become pygmies of epistemic agents possessing its own acquired worldview. In
order to solve this fragmentation, consensus-based weight synchronization communication is
being actively developed as a means of control to deal with AI drift. Niel and Bastard (2019)
believe that hardware AI systems become risky because of incoherent cognitive silos without
coordinated management of the lifecycle, which have unpredictable behavior. Therefore, the
history of embedded AI development has to be regarded not only as one engineering project but
also as a thoughtful process of conversation between firmware stability, learning flexibility, and
overall agreement between the systems.
AI Ethics & Governance
The high rate of artificial intelligence expansion in the public and the private sector has
prompted the demand of all inclusive governance models that facilitate innovation and
accountability. Ethical AI governance ceases being an abstract philosophical discussion, and it
becomes a regulatory imperative, especially as the decisions made by machines influence
employment, health care access and trial litigation more and more. Wirtz et al. (2020) state that
governance should shift towards reactive compliance to avoiding risks, which means proactive
compliance, ethical constraints, which should be embedded in the technical design and not in the
support documents of oversight. Transparency mechanisms like tools to interpret models and
logs of decision traceability are included in the core components of this transformation and allow
interrocomputer rationale use by external auditors instead of accepting opaque outputs.
Nevertheless, Mueller et al. (2019) point out that explainability is not enough when it turns into a
performative instead of a corrective process. Governance can only be true by having enforceable
escalation processes whereby anomalies that are detected can lead to intervention by the human
34
beings and not just observation. The AI governance should therefore become a hybrid regulation
model in which human control works not as an exception but as an ongoing complementary
control.
Bias mitigation is one of the most ageless ethical dilemmas in AI governance because
statistical differences inherent to training data may inadvertently bring about social inequality.
Leavy (2018) states that development team diversity is equally vital as the diversity of datasets,
as homogeneous engineering culture simply does not see patterns of exclusion that do not fit its
perception of the world. According to Niel and Bastard (2019), in medical diagnostics with high
stakes, minority demographics are overrepresented in biased model predictions, which negatively
impact the social trust in algorithmic decision systems. Coming models of governance should
therefore entail the introduction of demographic performance benchmarking as a reporting
measure and not evaluation measures. Guzman and Lewis (2020) warn that the aspect of
inequality increases further through the communicative asymmetry between the AI system and
its users since marginalized groups often lack literacy to challenge the authority of the algorithm.
Therefore, AI implementation should entail avenues of accountable user access, so that the
governance is based not just in the equity of the model, but also on procedural justice. In this
regard, AI ethics resembles the constitutional law: its legitimacy is not based on goodwill but
rather on the ability to challenge.
When AI systems are to be held accountable, it should be the case that the owners who
benefit from the decision have a clear understanding of the outcomes. However, the existing
legal frameworks find it difficult to pinpoint who is responsible when models operate
autonomously. In their work, Wirtz et al. (2020) present a hierarchical liability scheme in which
35
the fault is shared among the providers of data, the creators of the algorithm, and the
stakeholders for deployment based on their degree of influence on the generation of the output.
Nevertheless, such successive layers of attribution may have the effect of lessening rather than
increasing the clarity of accountability. Mueller et al. (2019) suggest that the concept of
accountability should be subordinated to the one of decision comprehensibility, whereby people
affected by the decision not only learn what the decision is but also understand why and by
whom it was made. On top of that, this interpretive clarity can be seen as the moral basis from
which legal remedies may be derived. According to Chatterjee (2020), in the absence of
interpretability, AI governance becomes a ritual of mock supervision showing no real control.
Thus, transparency audits ought to be the norm of technical checkpoints, which can be carried
out regularly, rather than being post-hoc evaluations initiated only when harm is done. The
management of affairs, consequently, has to turn into a finely tuned and flexible discipline that
not only foresees modes of failure but also takes steps to prevent them rather than merely judging
them.
Ethical governance of AI also requires looking at the knowledge theories that are implied
in AI systems, especially those that favor measurable things over non-measurable reasoning.
Rachmad (2016) stated that AI decision frameworks usually mirror reductionist views of
intelligence, simplifying complex human values into scalar optimization objectives. The use of
such instrumental logic is ethically problematic when, for example, it is employed in criminal
risk assessment or welfare distribution, areas in which human dignity cannot be numerically
abstracted without being distorted. Guzman and Lewis (2020) point out that the interaction
between AI and its users should be supported by the context, which recognizes the uncertainty
and moral ambiguity instead of hiding them under the cover of pseudo-scientific accuracy. Wirtz
36
et al. (2020) recommend that governing bodies should take the precautionary principle, thus,
limiting the use of AI in normative areas until interpretive validation is obtained. Therefore,
ethical AI governance is also about epistemic humility besides being a regulatory enforcement,
which involves being aware of the fact that algorithmic reasoning is fundamentally unsuitable for
certain societal judgments.
AI in Face Recognition/Biometrics
Facial recognition systems rely on complex feature extraction algorithms that convert raw
facial images into high-dimensional vector embeddings, enabling computational comparison
based on geometric or deep neural similarity. However, the effectiveness of such systems is
highly contingent upon dataset diversity, as models trained predominantly on homogeneous
populations often struggle to generalize across age, ethnicity, or lighting variance. Leavy (2018)
argues that gender and racial disparities within facial recognition systems are not mere technical
oversights but reflections of broader social inequities embedded within data collection practices.
Niel and Bastard (2019) warn that such inaccuracies can have severe consequences in medical
and security domains where false identification may lead to misdiagnosis or wrongful exclusion.
Chatterjee (2020) emphasizes that model performance metrics must therefore be stratified by
demographic subgroup rather than aggregated, ensuring that precision is equitable rather than
statistically averaged. Without such fairness-aware evaluation protocols, biometric AI risks
reinforcing systemic bias under the guise of mathematical neutrality.
Accuracy by itself is not enough to allow the use of biometric surveillance technologies;
the main factors that determine their legitimacy are still transparency and the user's autonomy.
Mueller et al. (2019) point out that people whose facial recognition is handled by an automated
37
system must be informed not only that their data is being processed but also how their facial data
will be kept, analyzed, and even shared. Biometric identifiers are different from passwords or ID
cards in that they cannot be changed once the data is leaked, which makes consent frameworks
more ethically sensitive. Guzman and Lewis (2020) emphasize that facial recognition has
different communicative implications as it turns the passive observation into the active data
extraction, most of the time without any verbal communication. This change from being visible
to being countable raises significant philosophical questions about the essence of public identity.
Therefore, governance policies should differentiate between authentication systems that people
use willingly and surveillance infrastructures that are imposed upon them, thus ensuring that
situational-specific norms regulate the extent of technology use. The moral justification of
biometric AI is not only about making the right identification but also about recognizing the
ontological limits between recognition and monitoring.
Adversarial attacks are one of the biggest challenges to facial recognition systems which
are usually used for security purposes. These attacks undermine the mathematical sensitivity of
neural embeddings by making visual changes that are carefully designed. Such changes are
mostly invisible to humans but can lead to identity misclassification by the models and even
direct authentication bypass. In the paper by Deng et al. (2020), it is mentioned that edge-based
biometric devices are highly susceptible to attacks since their limited computational power
makes it very difficult to implement defensive redundancy layers. In their work, Nandy and
Biswas (2017) recommend adversarial training using reinforcement learning as a method that can
defend against this threat. Such training will enable the models to become resistant to
perturbation strategies through attack simulation. Nevertheless, Mueller et al. (2019) warn that
the capability of the model to withstand adversaries should not at the same time compromise the
38
clarity with which it can be interpreted, as heavily defensive architectures might make the
internal decision logic less accessible. Hence, the strengthening of biometric security should not
only be about the technical aspects of the defense but also about maintaining the understanding
of the defense process. With the escalation of the attack techniques, security should not just rely
on the static encryption of data but have to take behavioral validation methods that are dynamic
into consideration. Such methods include liveness detection and multi-modal cross-referencing.
Identification should not be considered as a definitive match but rather as a probabilistic
negotiation between trust and caution.
The pervasive use of facial recognition in public infrastructure has caused jurisdictional
tensions that differ in terms of ownership and control of biometric repositories. According to
Wirtz et al. (2020), governance should not be based only on the institutional policy as a
centralized power structure can still prioritize civil liberties less than operational efficiency.
Leavy (2018) states that gender and racial minority groups misidentified more than others, so
consultation with the public becomes inevitable before massive deployment. Chatterjee (2020)
introduces the idea of federated identity systems where biometric data stays encrypted locally on
user devices and not in a centralized institutional database. These systems are similar to the
privacy-preserving medical systems referred to by Niel and Bastard (2019), where the sensitive
data is handled locally, and only the encoded results are shared. On the other hand, decentralized
storage makes it difficult to determine legal accountability in the case of a dispute. Guzman and
Lewis (2020) argue that thus, biometric governance should be a matter of dual sovereignty: on
the one hand, individuals having custodial rights over their data and on the other hand, oversight
agencies being entitled to audit misuse. This delicate balance is what constitutes the legitimacy
of future biometric infrastructures.
39
Facial recognition is still one of the most powerful means of authentication in the recent
times. It has the potential to completely remove the inconveniences of access control and make
the overall operations more efficient in different sectors. Nevertheless, this should not be the case
that the arrival of technology leads to the disappearance of human control, rather it should be
seen as the change in the way we distribute cognitive tasks by controlled automation. Mueller et
al. (2019) state that a cooperative AI framework is the best solution where biometric verification
is merely a recommendation and not an absolute decision, thereby permitting human operators to
handle the cases that are unclear. Niel and Bastard (2019) articulate comparable concepts in AI-
aided medical diagnostics, whereby the algorithmic suspicion leads to the further investigation
and not the final decision. Chatterjee (2020) points out that the morally correct biometric AI of
the future is one that acts as a mediator rather than a controller of identity. Consequently, the use
of facial recognition should be layered devices that confirm the identity of the users where the
latter should be allowed to challenge the results, ask for explanations, or request different ways
for identification. Biometric intelligence can only be in harmony with democratic ideals if it is
recognition done by a governance that can be challenged.
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References
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Jia, Q., Guo, Y., Li, R., Li, Y., & Chen, Y. (2018). A conceptual artificial intelligence
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Leavy, S. (2018, May). Gender bias in artificial intelligence: The need for diversity and gender
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