Design a multi-cycle implementation of the reduced MIPS architecture
casi
ECE449-Session_12.pptBasic Assumptions
- Clock faster than Single-Cycle CPU
- Clock speed now limited by propagation delays
- e.g. Instruction Fetch limited by memory cycle time
- Single Memory Unit
- Classical Von Neuman Structure
- Memory stores both instructions and data
- Basic Operations for instructions
- Instruction Fetch – get instruction from memory
- Instruction Decode – determine what instruction was fetched
- Causes a “branch” in the control logic to implement actions for this instruction
- Operand Fetch – get the operands for the instruction
- Execute – Perform the instruction operations
- Memory Cycle – fetch or save data
- Register Write – Save data in register file
Multi-cycle CPU Design
- Reference Chapter 7 in text
Instruction Analysis
| Inst. Type | Fetch | Decode | Operand Fetch | Execution | Memory Access | Register Write |
| R-type | IR <= M[PC] | ADD | Reg[rs], Reg[rt] | Reg[rs] + Reg[rt] | Reg[rd]<= r | |
| SUB | Reg[rs] - Reg[rt] | |||||
| AND | Reg[rs] & Reg[rt] | |||||
| OR | Reg[rs] | Reg[rt] | |||||
| XOR | Reg[rs] ^ Reg[rt] | |||||
| SLL | Reg[rd], Reg[rt], sa | Reg[rt] << sa | ||||
| SRL | Reg[rt] >> sa | |||||
| SRA | sxt(Reg[rt]) >> sa | |||||
| JR | Reg[rs] | PC <= Reg[rs] | ||||
| J-type | J | PC <= address | ||||
| JAL | Reg[31] <= PC + 8 PC <= address | |||||
| Reg[31] <= PC + 8 |
Instruction Analysis (cont)
| Inst. Type | Fetch | Decode | Operand Fetch | Execution | Memory Access | Register Write |
| I-type | IR <= M[PC] | ADDI | Reg[rs], Immediate | Reg[rs] + Imm | Reg[rt] <= r | |
| ANDI | Reg[rs] & Imm | |||||
| ORI | Reg[rs] | Imm | |||||
| XORI | Reg[rs] ^ Imm | |||||
| LW | Reg[rs], offset | MA <= Reg[rs} + offset | M[MA] | Reg[rt] <= M[MA] | ||
| SW | M[MA] <= Reg[rt] | |||||
| BEQ | Reg[rs], Reg[rt], offset | if (eq):PC <= offset If(neq) PC <= PC + 4 | ||||
| BNE | if (neq):PC <= offset If(eq) PC <= PC + 4 | |||||
| LUI | Reg[rt], immediate | Imm<<16 | Reg[rt] <= Imm<<16 |
Notes
- Fetch identical for all instructions
- Operands are available in the register file or the instruction
- Load word and Store Word require an additional memory action
Single-Cycle Fetch Diagram
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Fetch Diagram
- Fetch begins with the first clock edge loading the PC
- The memory cycles and the data are available
- The PC is sent to the ALU to be incremented by 4
- The next clock will load the Instruction Register (IR)
How Fast will it run
- Issue
- Will this approach yield performance improvement?
- The text (Table 7.1) implies that the expected number of clock cycles per instruction will be ~ 4.
- This implies that we need to clock the processor at four times the rate to equal the performance of the single-cycle machine
- Test by implementing the Fetch Diagram
- Need the following modules
- Two 32-bit registers with clock and write enable
- 32-bit x 32 word memory
- Control unit
- Two 32-bit x 4 multiplexers
- One 32-bit x 2 multiplexer
- ALU
Benchmark Instruction Mix Analysis
- Reference Hennessy and Patterson, Computer Architecture: A Quantitative Approach
- Average results of five SPECint 2000 benchmarks
- Chart implies our breakeven cycle time is 4.76 nsec or 210 MHz clock
| Instruction | Avg Occur | Cycles/Inst | Avg cycles |
| Load | 27% | 5 | 1.35 |
| Store | 11% | 5 | 0.55 |
| Add | 19% | 4 | 0.76 |
| Sub | 3% | 4 | 0.12 |
| Compare | 5% | 4 | 0.2 |
| Load imm | 2% | 4 | 0.08 |
| Cond Branch | 12% | 3 | 0.36 |
| Jump | 1% | 2 | 0.02 |
| Call | 1% | 2 | 0.02 |
| Return | 1% | 2 | 0.02 |
| Shift | 2% | 4 | 0.08 |
| And | 4% | 4 | 0.16 |
| Or | 9% | 4 | 0.36 |
| Xor | 3% | 4 | 0.12 |
| Totals | 100% | 4.2 |
Cyclone IV E Memory Spec
General Register
Memory
Part of the generated code
Control Unit
Four input 32-bit Mux
Two input 32-bit Mux
ALU
CPU
Completed Fetch Unit
MIF File for testing
Test Results at 100 MHz
Test Results at 200 MHz
Test Results at 185 Mhz
Instruction Decode and Operand Fetch
- Information for this state (Decode) contained in IR and RegFile
- Do these functions in one clock cycle
- Expand the hardware to include the following
- register file with output registers
- Sign extend and shift modules for immediate addresses
- Output register for ALU
- Extend the control unit to receive op and func fields from IR
Operations
- If the instruction is NOT J, JAL, or JR
- A <= RegisterFile[rs]
- B <= Register File[rd]
- C <= PC =sign_extend(offset) << 2
- Moves data from register file to output buffer registers
- Moves immediate address to register C
Control Unit for Decode (less J, JAL, and JR)
Instruction Decode and Operand Fetch (Cont)
- Jump, Jump and Link, and Jump Register complete execution in the Decode cycle.
Operations for J, JAL, and JR
- Jump (J)
- PC <= {PC[31:28], address, 2’b00}
- Jump and Link (JAL)
- RegisterFile[31] <= PC
- PC <= {PC[31:28], address, 2’b00}
- Jump Register (JR)
- PC <= RegisterFile[rs]
Completed Control Unit for Decode
Simulation at 200 MHz
Execution Cycle
- Branch Instructions
- BEQ: if (A == B) PC <= C else PC <= PC +4
- BNE: if (A != B) PC <= C else PC <= PC +4
- Branch address was placed in register C during the Decode Cycle
- ALU compares A and B using XOR
- text 7.1.3 says SUB but the included code uses XOR
- XOR was used in the Single-Cycle implementation as well
- If the results are equal, ALU generates zero (z) signal
- Branch instructions complete in this cycle
Diagram for Branch Instructions
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Execution Cycle (Cont)
- Other instructions perform the following
- ADD/SUB/AND/OR/XOR: C <= A op B where op is the indicated computational operation
- SLL: C <= B << sa
- SRL: C <= B >> sa
- SRA: C <= signed(B) >>> sa
- ADDI: C <= A + sign_ext(immediate)
- ANDI/ORI/XORI: C <= A op zero_ext(immediate)
- LUI: C <= immediate << 16
- LW/SW: C <= A + sign_ext(offset)
- In the case of computational and LUI instructions , results are now in register C
- For the load and store instructions, memory address is in register C
Block Diagram
Control Unit Update
Memory Access Cycle
- Only used by LW and SW instructions
- LW: DR <= Memory[C]
- SW: Memory[C] <= B
- DR is the register to buffer data output from memory
- Diagram for Execution Cycle added DR and the data path from C to the memory
Control Unit Update for Memory Access Cycle
Write Back Cycle
- Instructions that place data in the Register File are Completed in this cycle
- ADD/SUB/AND/OR/XOR/SLL/SRL/SRA
- RegisterFile[rd] <= C
- ADDI/ANDI/ORI/XORI/LUI
- RegisterFile[rt] <= C
- LW
- RegisterFile[rt] <= DR
Block Diagram for Write Back Cycle
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Control Unit Update for Write Back Cycle
Complete Diagram
Implementation
| Module Name | Function and Use | Source |
| gen_reg | General Register with we – PC, IR | JGW |
| dff32 | General Register no we – DR, A, B, C | Text |
| mux2x32 | Two-input, 32-bit Mux – MA_MUX, M2_REG_MUX, JAL_MUX, A/SA_MUX, ALU_A_MUX | Text |
| mux4x32 | Four-input 32-bit Mux – ALU_B_MUX, NXTPC_MUX | Text |
| regaddr_mux | JGW | |
| regfile | 32-word x 32-bit register file | Text |
| signext | Sign Extender Module | JGW |
| alu | ALU | Text |
| control | Control Unit | JGW |
| Memory | 32 word x 32-bit memory with registered inputs and unregistered output – initialize with Text MIF file (Sec 7.4.2) | Altera/JGW/Text |
Gen_Reg Code
Register Address MUX
Sign Extender
Control Unit
Complete System
- Following the approach in the text
- Created two modules – CPU and memory
- Signal names slightly different in my code
- 0
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CPU Module
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Complete Computer
- Exported Memory Address (MA) and Instruction Register (IR) for testing
Test Program
Results
- Appears to be cycling – sim clock set to 100 Mhz
- Above is logical sim
- Not yet running at 100 MHz in sim
- Below is timing sim running at 60 Mhz
