homework assignment

R1

R

S

1

THRES

R

R

R

TRIG 2

1

GND

DISCH 7

3 OUT

6

VDD 8

5 CONT RESET

4

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Reference Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC555 SLFS043H – SEPTEMBER 1983 – REVISED AUGUST 2016

TLC555 LinCMOS™ Timer

1

1 Features 1• Very Low Power Consumption:

– 1 mW Typical at VDD = 5 V • Capable of Operation in Astable Mode • CMOS Output Capable of Swinging Rail to Rail • High Output Current Capability

– Sink: 100 mA Typical – Source: 10 mA Typical

• Output Fully Compatible With CMOS, TTL, and MOS

• Low Supply Current Reduces Spikes During Output Transitions

• Single-Supply Operation From 2 V to 15 V • Functionally Interchangeable With the NE555;

Has Same Pinout • ESD Protection Exceeds 2000 V Per MIL-STD-

883C, Method 3015.2 • Available in Q-Temp Automotive

– High-Reliability Automotive Applications – Configuration Control and Print Support – Qualification to Automotive Standards

2 Applications • Precision Timing • Pulse Generation • Sequential Timing • Time Delay Generation • Pulse Width Modulation • Pulse Position Modulation • Linear Ramp Generator

Simplified Schematic

3 Description The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic, and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip- flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM)

TLC555C

SOIC (8) 4.9 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm SOP (8) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm

TLC555I SOIC (8) 4.90 mm × 3.91 mm PDIP (8) 9.81 mm × 6.38 mm

TLC555M LCCC (20) 8.89 mm × 8.89 mm CDIP (8) 9.60 mm × 6.67 mm

TLC555Q SOIC (8) 4.90 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

2

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Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison Table ..................................... 3 6 Pin Configuration and Functions ......................... 3 7 Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6 7.2 Recommended Operating Conditions ....................... 6 7.3 Thermal Information .................................................. 6 7.4 Electrical Characteristics: VDD = 2 V for TLC555C,

VDD = 3 V for TLC555I ............................................... 7 7.5 Electrical Characteristics: VDD = 5 V......................... 8 7.6 Electrical Characteristics: VDD = 15 V..................... 11 7.7 Electrical Characteristics: VDD = 5 V ...................... 14 7.8 Typical Characteristics ............................................ 14

8 Detailed Description ............................................ 15 8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 15 8.3 Feature Description................................................. 15 8.4 Device Functional Modes........................................ 19

9 Application and Implementation ........................ 20 9.1 Application Information............................................ 20 9.2 Typical Applications ................................................ 20

10 Power Supply Recommendations ..................... 26 11 Layout................................................................... 27

11.1 Layout Guidelines ................................................. 27 11.2 Layout Example .................................................... 27

12 Device and Documentation Support ................. 28 12.1 Receiving Notification of Documentation Updates 28 12.2 Community Resources.......................................... 28 12.3 Trademarks ........................................................... 28 12.4 Electrostatic Discharge Caution ............................ 28 12.5 Glossary ................................................................ 28

13 Mechanical, Packaging, and Orderable Information ........................................................... 28

4 Revision History

Changes from Revision G (November 2008) to Revision H Page

• Added Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................................................................................................... 1

• Deleted Continuous total power dissipation and lead temperature parameters from Absolute Maximum Ratings ............... 6 • Changed values in the Thermal Information table to align with JEDEC standards................................................................ 6 • Deleted Dissipation Ratings table .......................................................................................................................................... 6

1

2

3

4

5

6

7

NC

OUT

NC

RESET

TRIG

NC

GND

THRES

NC

CONT

DISCH

NC

V DD

NC

14

13

12

11

10

9

8

GND

TRIG DISCH

THRES

CONT

OUT

RESET

1

2

3

4

8

7

6

5

V DD

3

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5 Device Comparison Table

DEVICE TA VDD

RANGE SMALL

OUTLINE (D)

CHIP CARRIER

(FK)

CERAMIC DIP (JG)

PLASTIC DIP (P)

SSOP (PS)

TSSOP (PW)

TLC555C 0°C to 70°C 2 V to 15 V ✓ — — ✓ ✓ ✓ TLC555I –40°C to 85°C 3 V to 15 V ✓ — — ✓ — — TLC555M –55°C to 125°C 5 V to 15 V — ✓ ✓ — — — TLC555Q –40°C to 125°C 5 V to 15 V ✓ — — — — —

6 Pin Configuration and Functions

TLC555C: D, P, and PS Packages 8-Pin SOIC, PDIP, SOP

Top View

TLC555C: PW Package 14-Pin TSSOP

Top View

Pin Functions: TLC555C PIN

I/O DESCRIPTION NAME

SOIC, PDIP, SOP

TSSOP

CONT 5 8 I Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitorconnection. DISCH 7 12 O Open collector output to discharge timing capacitor GND 1 1 Ground

NC — 2, 4, 6,9, 11, 13 — No internal connection

OUT 3 5 O High current timer output signal RESET 4 7 I Active low reset input forces output and discharge low THRES 6 10 I End of timing input. THRES > CONT sets output low and discharge low. TRIG 2 3 I Start of timing input. TRIG < ½ CONT sets output high and discharge open. VDD 8 14 — Power-supply voltage

GND

TRIG DISCH

THRES

CONT

OUT

RESET

1

2

3

4

8

7

6

5

V DD

4

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TLC555I: D and P Packages 8-Pin SOIC, PDIP

Top View

Pin Functions: TLC555I PIN

I/O DESCRIPTION NAME SOIC, PDIP CONT 5 I Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection. DISCH 7 O Open-collector output to discharge timing capacitor GND 1 — Ground OUT 3 O High current timer output signal RESET 4 I Active low reset input forces output and discharge low THRES 6 I End of timing input. THRES > CONT sets output low and discharge low. TRIG 2 I Start of timing input. TRIG < ½ CONT sets output high and discharge open. VDD 8 — Power-supply voltage

GND

TRIG DISCH

THRES

CONT

OUT

RESET

1

2

3

4

8

7

6

5

V DD

N C

G N

D

N C

V D

D

N C

4

5

6

7

8

9 3

1 0

2

1 1

1

1 2

2 0

1 3

1 9

18

17

16

15

14

NC NC

DISCH

NC

THRES

NC

N C

R E

S E

T

N C

C O

N T

N C

TRIG

NC

OUT

NC

GND

TRIG DISCH

THRES

CONT

OUT

RESET

1

2

3

4

8

7

6

5

V DD

5

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TLC555M: JG Package 8-Pin CDIP Top View

TLC555M: FK Package 20-Pin LCCC

Top View

Pin Functions: TLC555M PIN

I/O DESCRIPTION NAME LCCC CDIP

CONT 12 5 I Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.

DISCH 17 7 O Open-collector output to discharge timing capacitor

GND 2 1 — Ground

NC 1, 3, 4, 6, 8, 9, 11, 13, 14,

16, 18, 19 — — No internal connection

OUT 7 3 O High current timer output signal

RESET 10 4 I Active low reset input forces output and discharge low

THRES 15 6 I End of timing input. THRES > CONT sets output low and discharge low.

TRIG 5 2 I Start of timing input. TRIG < ½ CONT sets output high and discharge open.

VDD 20 8 — Power-supply voltage

TLC555Q: D Package 8-Pin SOIC Top View

Pin Functions: TLC555Q PIN

I/O DESCRIPTION NAME SOIC

CONT 5 I Controls comparator thresholds, Outputs 2/3 VDD, allows bypass capacitor connection

DISCH 7 O Open-collector output to discharge timing capacitor

GND 1 — Ground

OUT 3 O High current timer output signal

RESET 4 I Active low reset input forces output and discharge low

THRES 6 I End of timing input. THRES > CONT sets output low and discharge low

TRIG 2 I Start of timing input. TRIG < ½ CONT sets output high and discharge open

VDD 8 — Power supply voltage

6

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network GND.

7 Specifications

7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

Voltage Supply, VDD

(2) 18 V Input, any input −0.3 VDD V

Current Sink, discharge or output 150 mA Source, output, IO 15 mA

Temperature Operating, TA

C-suffix 0 70 °C I-suffix –40 85 °C Q-suffix –40 125 °C M-suffix –55 125 °C

Case, for 60 seconds FK package –65 150 °C Storage, Tstg –65 150 °C

7.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT Supply voltage, VDD 2 15 V

Operating free-air temperature, TA

TLC555C 0 70 °C TLC555I –40 85 °C TLC555M –55 125 °C TLC555Q –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.3 Thermal Information

THERMAL METRIC (1)

TLC555

UNITD(SOIC) FK

(LCCC) JG

(CDIP) P

(PDIP) PS

(SOP) PW

(TSSOP) 8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 113 n/a 120 58 120 135 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58 37 81 48 72 61 °C/W RθJB Junction-to-board thermal resistance 55 36 110 35 69 77 °C/W

ψJT Junction-to-top characterization parameter 11 n/a 45 26 32 12 °C/W

ψJB Junction-to-board characterization parameter 54 n/a 103 35 68 77 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 4.3 31 n/a n/a n/a °C/W

7

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(1) Full range is 0°C to 70°C the for TLC555C, and −40°C to 85°C for the TLC555I. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.

(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

7.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

VIT Threshold voltage

25°C TLC555C 0.95 1.33 1.65

V TLC555I 1.6 2.4

Full range TLC555C 0.85 1.75

V TLC555I 1.5 2.5

IIT Threshold current

25°C TLC555C 10

pA TLC555I 10

Max TLC555C 75

pA TLC555I 150

VI(TRIG) Trigger voltage

25°C TLC555C 0.4 0.67 0.95

V TLC555I 0.71 1 1.29

Full range TLC555C 0.3 1.05

V TLC555I 0.61 1.39

II(TRIG) Trigger current

25°C TLC555C 10

pA TLC555I 10

Max TLC555C 75

pA TLC555I 150

VI(RESET) Reset voltage

25°C TLC555C 0.4 1.1 1.5

V TLC555I 0.4 1.1 1.5

Full range TLC555C 0.3 2

V TLC555I 0.3 1.8

Control voltage (open-circuit) as a percentage of supply voltage Max

TLC555C 66.7%

TLC555I 66.7%

Discharge switch on-stage voltage

IOL = 1 mA, 25°C TLC555C 0.03 0.2

V TLC555I 0.03 0.2

IOL = 1 mA, Full range TLC555C 0.25

V TLC555I 0.375

Discharge switch off-stage current

25°C TLC555C 0.1

nA TLC555I 0.1

Max TLC555C 0.5

nA TLC555I 120

VOH High-level output voltage

IOH = –300 µA, 25°C TLC555C 1.5 1.9

V TLC555I 2.5 2.85

IOH = –300 µA, Full range

TLC555C 1.5 V

TLC555I 2.5

VOL Low-level output voltage

IOL = 1 mA, 25°C TLC555C 0.07 0.3

V TLC555I 0.07 0.3

IOL = 1 mA, Full range TLC555C 0.35

V TLC555I 0.4

IDD Supply current (2)

25°C TLC555C 250

µA TLC555I 250

Full range TLC555C 400

µA TLC555I 500

8

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(1) Full range is 0°C to 70°C the for TLC555C, −40°C to 85°C for the TLC555I, −40°C to 125°C for the TLC555Q, and −55°C to 125°C for the TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.

7.5 Electrical Characteristics: VDD = 5 V over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

VIT Threshold voltage

25°C

TLC555C 2.8 3.3 3.8

V TLC555I 2.8 3.3 3.8

TLC555M 2.8 3.3 3.8

TLC555Q 2.8 3.3 3.8

Full range

TLC555C 2.7 3.9

V TLC555I 2.7 3.9

TLC555M 2.7 3.9

TLC555Q 2.7 3.9

IIT Threshold current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

VI(TRIG) Trigger voltage

25°C

TLC555C 1.36 1.66 1.96

V TLC555I 1.36 1.66 1.96

TLC555M 1.36 1.66 1.96

TLC555Q 1.36 1.66 1.96

Full range

TLC555C 1.26 2.06

V TLC555I 1.26 2.06

TLC555M 1.26 2.06

TLC555Q 1.26 2.06

II(TRIG) Trigger current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

VI(RESET) Reset voltage

25°C

TLC555C 0.4 1.1 1.5

V TLC555I 0.4 1.1 1.5

TLC555M 0.4 1.1 1.5

TLC555Q 0.4 1.1 1.5

Full range

TLC555C 0.3 1.8

V TLC555I 0.3 1.8

TLC555M 0.3 1.8

TLC555Q 0.3 1.8

II(RESET) Reset current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

9

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Electrical Characteristics: VDD = 5 V (continued) over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

Control voltage (open circuit) as a percentage of supply voltage Max

TLC555C 66.7%

TLC555I 66.7%

TLC555M 66.7%

TLC555Q 66.7%

Discharge switch on-stage voltage

IOL = 10 mA, 25°C

TLC555C 0.14 0.5

V TLC555I 0.14 0.5

TLC555M 0.14 0.5

TLC555Q 0.14 0.5

IOL = 10 mA, Full range

TLC555C 0.6

V TLC555I 0.6

TLC555M 0.6

TLC555Q 0.6

Discharge switch off-stage current

25°C

TLC555C 0.1

nA TLC555I 0.1

TLC555M 0.1

TLC555Q 0.1

Max

TLC555C 0.5

nA TLC555I 120

TLC555M 120

TLC555Q 120

VOH High-level output voltage

IOH = –1 µA, 25°C

TLC555C 4.1 4.8

V TLC555I 4.1 4.8

TLC555M 4.1 4.8

TLC555Q 4.1 4.8

IOH = –1 µA, Full range

TLC555C 4.1

V TLC555I 4.1

TLC555M 4.1

TLC555Q 4.1

VOL Low-level output voltage

IOL = 8 mA, 25°C

TLC555C 0.21 0.4

V TLC555I 0.21 0.4

TLC555M 0.21 0.4

TLC555Q 0.21 0.4

IOL = 8 mA, Full range

TLC555C 0.5

V TLC555I 0.5

TLC555M 0.6

TLC555Q 0.6

10

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Electrical Characteristics: VDD = 5 V (continued) over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

VOL Low-level output voltage

IOL = 5 mA, 25°C

TLC555C 0.13 0.3

V TLC555I 0.13 0.3

TLC555M 0.13 0.3

TLC555Q 0.13 0.3

IOL = 5 mA, Full range

TLC555C 0.4

V TLC555I 0.4

TLC555M 0.45

TLC555Q 0.45

IOL = 3.2 mA, 25°C

TLC555C 0.08 0.3

V TLC555I 0.08 0.3

TLC555M 0.8 0.3

TLC555Q 0.8 0.3

IOL = 3.2 mA, Full range

TLC555C 0.35

V TLC555I 0.35

TLC555M 0.4

TLC555Q 0.4

IDD Supply current (2)

25°C

TLC555C 170 350

µA TLC555I 170 350

TLC555M 170 350

TLC555Q 170 350

Full range

TLC555C 500

µA TLC555I 600

TLC555M 700

TLC555Q 700

11

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(1) Full range is 0°C to 70°C for TLC555C, −40°C to 85°C for TLC555I, −40°C to 125°C for the TLC555Q, and −55°C to 125°C for TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.

7.6 Electrical Characteristics: VDD = 15 V over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

VIT Threshold voltage

25°C

TLC555C 9.45 10 10.55

V TLC555I 9.45 10 10.55

TLC555M 9.45 10 10.55

TLC555Q 9.45 10 10.55

Full range

TLC555C 9.35 10.65

V TLC555I 9.35 10.65

TLC555M 9.35 10.65

TLC555Q 9.35 10.65

IIT Threshold current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

VI(TRIG) Trigger voltage

25°C

TLC555C 4.65 5 5.35

V TLC555I 4.65 5 5.35

TLC555M 4.65 5 5.35

TLC555Q 4.65 5 5.35

Full range

TLC555C 4.55 5.45

V TLC555I 4.55 5.45

TLC555M 4.55 5.45

TLC555Q 4.55 5.45

II(TRIG) Trigger current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

VI(RESET) Reset voltage

25°C

TLC555C 0.4 1.1 1.5

V TLC555I 0.4 1.1 1.5

TLC555M 0.4 1.1 1.5

TLC555Q 0.4 1.1 1.5

Full range

TLC555C 0.3 1.8

V TLC555I 0.3 1.8

TLC555M 0.3 1.8

TLC555Q 0.3 1.8

II(RESET) Reset current

25°C

TLC555C 10

pA TLC555I 10

TLC555M 10

TLC555Q 10

Max

TLC555C 75

pA TLC555I 150

TLC555M 5000

TLC555Q 5000

12

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Electrical Characteristics: VDD = 15 V (continued) over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

Control voltage (open circuit) as a percentage of supply voltage Max

TLC555C 66.7%

TLC555I 66.7%

TLC555M 66.7%

TLC555Q 66.7%

Discharge switch on-stage voltage

IOL = 100 mA, 25°C

TLC555C 0.77 1.7

V TLC555I 0.77 1.7

TLC555M 0.77 1.7

TLC555Q 0.77 1.7

IOL = 100 mA, Full range

TLC555C 1.8

V TLC555I 1.8

TLC555M 1.8

TLC555Q 1.8

Discharge switch off-stage current

25°C

TLC555C 0.1

nA TLC555I 0.1

TLC555M 0.1

TLC555Q 0.1

Max

TLC555C 0.5

nA TLC555I 120

TLC555M 120

TLC555Q 120

VOH High-level output voltage

IOH = –10 mA, 25°C

TLC555C 12.5 14.2

V TLC555I 12.5 14.2

TLC555M 12.5 14.2

TLC555Q 12.5 14.2

IOH = –10 mA, Full range

TLC555C 12.5

V TLC555I 12.5

TLC555M 12.5

TLC555Q 12.5

IOH = –5 mA, 25°C

TLC555C 13.5 14.6

V TLC555I 13.5 14.6

TLC555M 13.5 14.6

TLC555Q 13.5 14.6

IOH = –5 mA, Full range

TLC555C 13.5

V TLC555I 13.5

TLC555M 13.5

TLC555Q 13.5

IOH = –1 mA, 25°C

TLC555C 14.2 14.9

V TLC555I 14.2 14.9

TLC555M 14.2 14.9

TLC555Q 14.2 14.9

IOH = –1 mA, Full range

TLC555C 14.2

V TLC555I 14.2

TLC555M 14.2

TLC555Q 14.2

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Electrical Characteristics: VDD = 15 V (continued) over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT

(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

VOL Low-level output voltage

IOL = 100 mA, 25°C

TLC555C 1.28 3.2

V TLC555I 1.28 3.2

TLC555M 1.28 3.2

TLC555Q 1.28 3.2

IOL = 100 mA, Full range

TLC555C 3.6

V TLC555I 3.7

TLC555M 3.8

TLC555Q 3.8

IOL = 50 mA, 25°C

TLC555C 0.63 1

V TLC555I 0.63 1

TLC555M 0.63 1

TLC555Q 0.63 1

IOL = 50 mA, Full range

TLC555C 1.3

V TLC555I 1.4

TLC555M 1.5

TLC555Q 1.5

IOL = 10 mA, 25°C

TLC555C 0.12 0.3

V TLC555I 0.12 0.3

TLC555M 0.12 0.3

TLC555Q 0.12 0.3

IOL = 10 mA, Full range

TLC555C 0.4

V TLC555I 0.4

TLC555M 0.45

TLC555Q 0.45

IDD Supply current (2)

25°C

TLC555C 360 600

µA TLC555I 360 600

TLC555M 360 600

TLC555Q 360 600

Full range

TLC555C 800

µA TLC555I 900

TLC555M 1000

TLC555Q 1000

-75 -50 -25 0 25 50 75 100 125

1

2

4

7

10

20

40

70

100

D is

c h a rg

e S

w it c h O

n -S

ta te

R e s is

ta n c e (

) W

Temperature ( C)°

V = 15 V, I = 100 mADD O

V = 5 V, I = 10 mADD O

V = 2 V, I = 1 mADD O

600

500

400

300

200

100

0

0 2 4 6 8 10 12 14 16 18 20

Supply Voltage (V)

P ro

p a

g a

ti o

n D

e la

y T

im e

s (

n s )

tPLH (1)

tPHL

I 1 mA

C 0

T = 25 C

O(on)

L

A

³

»

°

14

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(1) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

7.7 Electrical Characteristics: VDD = 5 V At TA = 25°C, over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT Threshold voltage 2.8 3.3 3.8 V IIT Threshold current 10 pA VI(TRIG) Trigger voltage 1.36 1.66 1.96 V II(TRIG) Trigger current 10 pA VI(RESET) Reset voltage 0.4 1.1 1.5 V II(RESET) Reset current 10 pA

Control voltage (open circuit) as a percentage of supply voltage 66.7%

Discharge switch on-stage voltage IOL = 10 mA 0.14 0.5 v Discharge switch off-stage current 0.1 nA

VOH High-level output voltage IOH = –1 mA 4.1 4.8 V

VOL Low-level output voltage IOL = 8 mA 0.21 0.4 V IOL = 5 mA 0.13 0.3 V IOL = 3.2 mA 0.08 0.3 V

IDD Supply current (1) 170 350 µA

7.8 Typical Characteristics

Figure 1. Discharge Switch ON-State Resistance vs Free-Air Temperature

(1) The effects of the load resistance on these values must be taken into account separately.

Figure 2. Propagation Delay Times to Discharge Output from Trigger and Threshold Shorted Together

vs Supply Voltage

R1

R

S

1

THRES

R

R

R

TRIG 2

1

GND

DISCH 7

3 OUT

6

VDD 8

5 CONT RESET

4

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8 Detailed Description

8.1 Overview The TLC555 is a precision timing device used for general-purpose timing applications up to 2.1 MHz.

8.2 Functional Block Diagram

Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES.

8.3 Feature Description

8.3.1 Monostable Operation For monostable operation, any of these timers can be connected as shown in Figure 3. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.

− O

u tp

u t

P u

ls e

D u

ra ti

o n

− s

C − Capacitance − mF

10

1

10−1

10−2

10−3

10−4

1001010.10.01 10−5

0.001

t w

RA = 10 MW

RA = 10 kW

RA = 1 kW

RA = 100 kW

RA = 1 MW

V o

lt a g

e −

2 V

/d iv

Time − 0.1 ms/div

Capacitor Voltage

Output Voltage

Input Voltage

RA = 9.1 kW

CL�= 0.01�mF

RL = 1 kW

See Figure 9

VDD ( 5 V t o 1 5 V)

RA RL

Output

GND

OUT

VDDCONT

RESET

DISCH

THRES

TRIGInput

5 8

4

7

6

2

3

1

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Feature Description (continued)

Figure 3. Circuit for Monostable Operation

Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 4 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval.

Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used it must be connected to VCC.

Figure 4. Typical Monostable Waveforms Figure 5. Output Pulse Duration vs Capacitance

( )H L A Bperiod t t 0.693 R 2R C= + = +

( )L Bt 0.693 R C=

( )H A Bt 0.693 R R C= +

VDD

2/3 VDD

1/3 VDD

GND

tPHL

tPLH

tc(H) tc(L)

V o

lt a g

e −

1 V

/d iv

Time − 0.5 ms/div

t H

Capacitor Voltage

Output VoltagetL

RA = 5 kW RL = 1 kW

RB = 3 kW See Figure 12

C = 0.15 mF

GND

OUT

VDDCONT

RESET

DISCH

THRES

TRIG

C

RB

RA

Output

RL

0.01 FP

VDD (5 V to 15 V)

(see Note A)

NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications.

Open

5 8

4

7

6

2

3

1

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Feature Description (continued) 8.3.2 Astable Operation As shown in Figure 6, adding a second resistor, RB, to the circuit of Figure 3 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB.

This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.

Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications.

Figure 6. Circuit for Astable Operation Figure 7. Typical Astable Waveforms

Figure 8. Trigger and Threshold Voltage Waveform Figure 7 shows typical waveforms generated during astable operation. The output high-level duration tH and low- level duration tL can be calculated as follows:

(1)

(2)

Other useful relationships are shown below:

(3)

V o

lt a g

e −

2 V

/d iv

Time − 0.1 ms/div

Capacitor Voltage

Output Voltage

Input Voltage

VCC = 5 V

RA = 1250 W

C = 0.02 mF

See Figure 9

f −

F re

e -R

u n

n in

g F

re q

u e n

c y

− H

z

C − Capacitance − mF

100 k

10 k

1 k

100

10

1

1001010.10.01 0.1

0.001

RA + 2 RB = 10 MW

RA + 2 RB = 1 MW

RA + 2 RB = 100 kW

RA + 2 RB = 10 kW

RA + 2 RB = 1 kW

L B

H A B

t R Low-to-high ratio

t R R = =

+

H B

H L A B

t R Output waveform duty cycle 1

t t R 2R = = -

+ +

L B

H L A B

t R Output driver duty cycle

t t R 2R = =

+ +

( )A B

1.44 frequency

R 2R C »

+

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Feature Description (continued)

(4)

(5)

(6)

(7)

Figure 9. Free-Running Frequency

8.3.3 Frequency Divider By adjusting the length of the timing cycle, the basic circuit of Figure 6 can be made to operate as a frequency divider. Figure 10 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during the timing cycle.

Figure 10. Divide-by-Three Circuit Waveforms

THRES

CONT

DISCH

OUT

GND

COMPONENT COUNT Transistors Resistors

39 5

VDD

TRIG RESET

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(1) For conditions shown as MIN or MAX, use the appropriate value specified under Electrical Characteristics: VDD = 5 V .

8.4 Device Functional Modes Table 1 shows the device functional modes.

Table 1. Function Table RESET

VOLTAGE (1) TRIGGER VOLTAGE (1) THRESHOLD

VOLTAGE (1) OUTPUT DISCHARGE SWITCH

<MIN Irrelevant Irrelevant L On >MAX <MIN Irrelevant H Off >MAX >MAX >MAX L On >MAX >MAX <MIN As previously established

Figure 11. Equivalent Schematic (Each Channel)

VDD (5 V to 15 V)

DISCH

OUT VDDRESET

RL RA

A5T3644

C

THRES

GND

CONT

TRIG

Input

0.01 FP

Output

4 8

3

7

6

2

5

1

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9 Application and Implementation

NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information The TLC555 timer device uses resistor and capacitor charging delay to provide a programmable time delay or operating frequency. The Typical Applications section presents a simplified discussion of the design process.

9.2 Typical Applications

9.2.1 Missing-Pulse Detector The circuit shown in Figure 12 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 13.

Figure 12. Circuit for Missing-Pulse Detector

9.2.1.1 Design Requirements Input fault (missing pulses) must be input high. An input stuck low cannot be detected because the timing capacitor (C) remains discharged.

9.2.1.2 Detailed Design Procedure Choose RA and C so that RA× C > [maximum normal input high time]. RL improves VOH, but it is not required for TTL compatibility.

THRES GND

C

RARL

VDD (5 V to 15 V)

Output

DISCH

OUT

VDDRESET

TRIG

CONT Modulation

Input (see Note A)

Clock Input

NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered.

4 8

3

7

6

2

5

1

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Time − 0.1 ms/div

V o

lt a g

e −

2 V

/d iv

VDD = 5 V

RA = 1 kW

C = 0.1 mF

See Figure 15

Capacitor Voltage

Output Voltage

Input Voltage

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Typical Applications (continued) 9.2.1.3 Application Curve

Figure 13. Completed Timing Waveforms for Missing-Pulse Detector

9.2.2 Pulse-Width Modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 14 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 15 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used.

The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of modulation source voltage and impedance on the bias of the timer.

Figure 14. Circuit for Pulse-Width Modulation

V o

lt a g

e −

2 V

/d iv

Time − 0.5 ms/div

Capacitor Voltage

Clock Input Voltage

RA = 3 kW

C = 0.02 mF

RL = 1 kW

See Figure 18

Modulation Input Voltage

Output Voltage

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Typical Applications (continued) 9.2.2.1 Design Requirements The clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD, respectively. Modulation input can vary from ground to VDD. The application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is RC based with an negative exponential curve.

9.2.2.2 Detailed Design Procedure Choose RA and C so that RA × C = 1/4 [clock input period]. RL improves VOH, but it is not required for TTL compatibility.

9.2.2.3 Application Curve

Figure 15. Pulse-Width-Modulation Waveforms

9.2.3 Pulse-Position Modulation As shown in Figure 16, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and thereby the time delay of a free-running oscillator. Figure 17 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used.

RB Modulation

Input (see Note A)

CONT

TRIG

RESET VDD OUT

DISCH

VDD (5 V to 15 V)

RL RA

C

GND

THRES

NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered.

4 8

3

7

6

2

5

Output

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Typical Applications (continued)

The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of modulation source voltage and impedance on the bias of the timer.

Figure 16. Circuit for Pulse-Position Modulation

V o

lt a g

e −

2 V

/d iv

RA = 3 kW

RB = 500W

RL = 1 kW

See Figure 20

Capacitor Voltage

Output Voltage

Modulation Input Voltage

Time − 0.1 ms/div

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Typical Applications (continued) 9.2.3.1 Design Requirements Both DC- and AC-coupled modulation input changes the upper and lower voltage thresholds for the timing capacitor. Both frequency and duty cycle vary with the modulation voltage.

9.2.3.2 Detailed Design Procedure The nominal output frequency and duty cycle can be determined using formulas in Astable Operation. RL improves VOH, but it is not required for TTL compatibility.

9.2.3.3 Application Curve

Figure 17. Pulse-Position-Modulation Waveforms

9.2.4 Sequential Timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 18 shows a sequencer circuit with possible applications in many systems, and Figure 19 shows the output waveforms.

S

VDD

RESET VDD OUT

DISCH

GND

CONT

TRIG

4 8

3

7

6

1

5

2

THRES

RC

CC 0.01

CC = 14.7 FP RC = 100 k: Output C

RESET VDD OUT

DISCH

GND

CONT

TRIG

4 8

3

7

6

1

5

2

THRES

RB 33 k:

0.001

0.01 PF

CB = 4.7PF RB = 100 k:

Output BOutput ARA = 100 k: CA = 10 PF

PF 0.01

PF 0.001

33 k:RA

THRES

2

5

1

6

7

3

84

TRIG

CONT

GND

DISCH

OUT VDDRESET

PF

PF

CBCA

NOTE A: S closes momentarily at t = 0.

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Typical Applications (continued)

S closes momentarily at t = 0.

Figure 18. Sequential Timer Circuit

9.2.4.1 Design Requirements The sequential timer application chains together multiple monostable timers. The joining components are the 33-kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next monostable.

9.2.4.2 Detailed Design Procedure The timing resistors and capacitors can be chosen using this formula: tw = 1.1 × R × C.

V o

lt a g

e −

5 V

/d iv

t − Time − 1 s/div

See Figure 22

Output A

Output B

Output C

t = 0

twC = 1.1 RCCCtwC

twB = 1.1 RBCB

twA = 1.1 RACA twA

twB

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Typical Applications (continued) 9.2.4.3 Application Curve

Figure 19. Sequential Timer Waveforms

10 Power Supply Recommendations The TLC555 requires a voltage supply within 2 V to 15 V. Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1-μF ceramic in parallel with 1-μF electrolytic. Place the bypass capacitors as close as possible to the TLC555 and minimize the trace length.

GND

TRIG

OUT

RESET

VDD

DISCH

THRES

CONT

T L C 5 5 5

C4

C3

R1

C1

C2

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11 Layout

11.1 Layout Guidelines Standard PCB rules apply to routing the TLC555. The 0.1-μF ceramic capacitor in parallel with a 1-μF electrolytic capacitor must be as close as possible to the TLC555. The capacitor used for the time delay must also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.

Figure 20 is the basic layout for various applications. • C1—based on time delay calculations • C2—0.01-μF bypass capacitor for control voltage pin • C3—0.1-μF bypass ceramic capacitor • C4—1-μF electrolytic bypass capacitor • R1—based on time-delay calculations

11.2 Layout Example

Figure 20. Layout Example

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks LinCMOS, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1)

Package Type Package Drawing

Pins Package Qty

Eco Plan (2)

Lead/Ball Finish (6)

MSL Peak Temp (3)

Op Temp (°C) Device Marking (4/5)

Samples

TLC555CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL555C

TLC555CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL555C

TLC555CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL555C

TLC555CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL555C

TLC555CP ACTIVE PDIP P 8 50 Pb-Free (RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TLC555CP

TLC555CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS)

CU NIPDAU N / A for Pkg Type 0 to 70 TLC555CP

TLC555CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 P555

TLC555CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 P555

TLC555CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 P555

TLC555CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 P555

TLC555ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL555I

TLC555IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL555I

TLC555IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL555I

TLC555IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL555I

TLC555IP ACTIVE PDIP P 8 50 Pb-Free (RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TLC555IP

TLC555IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 TLC555IP

TLC555QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL555Q

PACKAGE OPTION ADDENDUM

www.ti.com 2-Feb-2016

Addendum-Page 2

Orderable Device Status (1)

Package Type Package Drawing

Pins Package Qty

Eco Plan (2)

Lead/Ball Finish (6)

MSL Peak Temp (3)

Op Temp (°C) Device Marking (4/5)

Samples

TLC555QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM TL555Q

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC555 :

PACKAGE OPTION ADDENDUM

www.ti.com 2-Feb-2016

Addendum-Page 3

• Automotive: TLC555-Q1

• Military: TLC555M

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Type

Package Drawing

Pins SPQ Reel Diameter

(mm)

Reel Width

W1 (mm)

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W (mm)

Pin1 Quadrant

TLC555CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLC555CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TLC555IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLC555QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLC555QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC555CDR SOIC D 8 2500 340.5 338.1 20.6

TLC555CPWR TSSOP PW 14 2000 367.0 367.0 35.0

TLC555IDR SOIC D 8 2500 340.5 338.1 20.6

TLC555QDR SOIC D 8 2500 367.0 367.0 38.0

TLC555QDRG4 SOIC D 8 2500 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 2

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