Digital Systems and Circuits - lab

EEE 425/591, ASU

Spring 2017

Lab #5

Due Sunday, April 9 nd

, 11:59PM

You may work in groups of up to 3 people. You can use this design in the final lab and in that lab

extra points will be given to the 3 designs with lowest EDP (Energy Delay Product) Value.

Submission: Prepare a concise report (< 5 pages) with important results only. You don’t have to

include the entire set of your circuit schematics or layout plots. Place the report in Assignment at

myasu with the filename as: EEE425_Lab_5_your name or EEE591_Lab_5_your name.

1 bit adder design

In this lab you are going to design a 1-bit adder with an architecture of your choice. For all

transistors L=30nm and VDD = 1.05V. For all input signals rise and fall times are 30ps (Tr = Tf = 30ps

between 0% and 100% VDD). Load for the sum output of the adder is going to be a FO4 of inverter

with Wn =420nm & Wp =640nm (Do not include inverters in the layout).

Please name your nets as,

Inputs: A, B, Cin Outputs: Cout, S

1) Create a schematic of the 1-bit adder with topology of your choice, use logical efforts to estimate the sizes in order to optimize delays. Please include your hand calculations in the report.

(For appropriate sizing of PMOS and NMOS in order to have PUN and PDN having the same drive

capability refer to lab-1)

2) Create a testbench in HSPICE and measure A-B to COUT, A-B to S and provide plots for the

worst cases (i.e. A to COUT, B to S). Also measure CIN to COUT and CIN to S and provide plots. Do

these measurement for 5 Corners (TT, SS, SF, FS and FF). Include your plots for TT corner for above

measurements and report measured values for every corner.

3) Draw the layout for 1-bit adder. Replace your schematic with the layout in the HSPICE testbench and repeat the measurements in (2) again for the same 5 corners. Please include your

plots and measurement results as in (2). Also include DRC & LVS pass screens with your layout

view.

4) Calculate the Energy – Delay Product (EDP) for 1-bit adder using layout design (Do not include the power of the load inverter). Report your area as well (Area should be measured as the smallest

rectangle encapsulating your layout without VDD and GND taps).