Complete my final exam. Electronic Engineering only
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final_exam_s17.docxName/Date:
Final Exam ECE 204-02 Electronic Devices, Spring 2017
Instructions:
· This is an open book/notes exam, however you must complete it on your own.
· Put ALL final answers on this sheet correct to 3 decimal places.
· Show all work & equations used on separate pages.
Print out this exam sheet and complete all analysis by hand on separate sheets of paper. Submit this examination via email by May 3rd, 2:00PM EST. Submit a single PDF document that contains this answer sheet and all additional work sheets. Ensure that the document looks professional; have all work laid out clearly and logically with scanned images appearing upright and legible.
You will only have one chance to upload your final exam. I will not accept multiple exam solutions, only the first one submitted. Feel free to submit early. Be sure to save enough time before the deadline to create the PDF document and send it to me.
Finally, bear in mind that I will have a zero tolerance policy for plagiarism from other students. If I believe cheating has occurred, all parties involved will receive zero points for the final exam.
The Honor Pledge By Students:
I understand that as a student of the University of Dayton, I am a member of our academic and social community. I recognize the importance of my education and the value of experiencing life in such an integrated community. I believe that the value of my education and degree is critically dependent upon the academic integrity of the university community, and so in order to maintain our academic integrity, I pledge to:
1. Complete this final examinations by the guidelines given to me by my instructors
2. Avoid plagiarism and any other form of misrepresenting someone else's work as my own
3. Adhere to the Standards of Conduct as outlined in the Academic Honor Code
_____________________ ______________________
Signature Date
1. Given the NMOS common source amplifier circuit in Figure 1 and Vt = 1.5 V, kn = 8m A/V2, |VA|=10 V, RD = 10 kΩ, RS = 500 Ω, VDD = 15 V, RG1 = 5 MΩ, RG2 = 1 MΩ, RL = 5 kΩ, and Rsig = 2.5 MΩ, determine the following.
a) [DC Analysis] Assume in saturation and find: VG = _______, VS = _______, VD = _______,
VGS = _______, VDS = _______, VOV = _______, ID = _______, IS = _______, and IG = _______.
Use your answers for VGS, VDS, VOV to prove “on” and in saturation mode:
b) [Small Signal Parameters] Find gm = _________ , ro = _________.
c) [Small Signal Model] Use π-model; draw the complete small signal equivalent circuit. Label the three terminals and the locations of Rin, Rout, vin, and vout.
d) [Small Signal Analysis] Find the following values: Rin = _________, Rout = _________,
AVO = _________, AV = _________, and GV = _________.
e) [Small Signal Analysis] If |vsig(peak)| = 10 mV, what is |vout(peak)| = ___________________ ?
Figure 1: NMOS common source amplifier circuit.
2. Given the npn BJT common emitter amplifier circuit in Figure 2 and VT = 25 mV, β = 100, r0 = ∞ Ω, RC = 10 kΩ, RE = 300 Ω, RL = 30 kΩ, Rsig = 6.31 kΩ, VCC = 24 V, IDC = 20 µA, and the device yields IC = 0.5 mA @ test voltage VBE = 0.7 V, determine the following. (HINT: Do not assume VBE = 0.7 in this configuration)
a) [DC Analysis] Assume in active mode and find: α = _______, IB = _______, IC = _______, IE = _______, VC = _______, VE = _______, VBE = _______, VB = _______, VCB = _______, VCE = _______, and IS =_______.
Use your answers above to confirm in active mode:
b) [Small Signal Parameters] Find gm = _________, rπ = _________, and re = _________.
c) [Small Signal Model] Use T-model to draw the complete small signal equivalent circuit below. Label the three terminals and the locations of Rin, Rout, vin, and vout.
d) [Small Signal Analysis] Find the following values: Rin = _________, Rout = _________,
AVO = _________, AV = _________, and GV = _________ .
e) [Small Signal Analysis] If |vsig(peak)| = 50 mV, what is |vout(peak)| = ___________________ ?
Figure 2: npn BJT common emitter amplifier circuit.
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