digital

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 1 Winter, 2017

NAME: _____________________________________ Due: 03/06/2017 Show your work. Answers without supporting work will not earn full credit. Ignore all flip-flop sets and resets. 1. Draw a five D flip-flop Johnson counter. Do not include forbidden

state detection. Assuming the flip-flops are initially all ones, show the successive states through the return to all ones.

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 2 Winter, 2017

2. Given the following circuit, generate its state chart and draw its

state diagram.

X Y A X+ Y+ Z DX DY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 3 Winter, 2017

PROBLEM #2, Continued:

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 4 Winter, 2017

3. Given the following state diagram, generate the corresponding

state chart including the D inputs. Also give the minimized equations for the D inputs and for the output, B. Let the state bits be labeled X and Y, the input A and the output B.

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 5 Winter, 2017

PROBLEM #3, Continued:

X Y A X+ Y+ B DX DY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

X / Y A 0 0 0 1 1 1 1 0 X / Y A 0 0 0 1 1 1 1 0

0 0 1 1

X / Y A 0 0 0 1 1 1 1 0

0 1

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 6 Winter, 2017

4. Complete the following partial state chart by showing the

necessary J and K inputs for the flip flops. Give the minimized equations for the J and K inputs and for the output, and draw the state diagram. The state bits are A and B, the input is C and the output is Z.

A B C A+ B+ Z JA KA JB KB 0 0 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 0 1 1

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 7 Winter, 2017

PROBLEM #4, Continued: A / B C 0 0 0 1 1 1 1 0 A / B C 0 0 0 1 1 1 1 0

0 0 1 1

A / B C 0 0 0 1 1 1 1 0 A / B C 0 0 0 1 1 1 1 0

0 0 1 1

A / B C 0 0 0 1 1 1 1 0

0 1

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 8 Winter, 2017

PROBLEM #4, Continued:

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 9 Winter, 2017

5. Given the following state diagram, generate the corresponding

state chart including the necessary J and K inputs. Also give the minimized equations for the J and K inputs and for the output. Let the state bits be labeled X, Y and Z, the input A and the output f.

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 10 Winter, 2017

PROBLEM #5, Continued:

X Y Z A X+ Y+ Z+ f JX KX JY KY JZ KZ 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

XY / ZA 0 0 0 1 1 1 1 0 XY / ZA 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 11 Winter, 2017

PROBLEM #5, Continued: XY / ZA 0 0 0 1 1 1 1 0 XY / ZA 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

XY / ZA 0 0 0 1 1 1 1 0 XY / ZA 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

XY / ZA 0 0 0 1 1 1 1 0

0 0 0 1 1 1 1 0

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 12 Winter, 2017

6. Design an 8-state state machine counter with the following

characteristics: • If the e (even) input is 1, the next state is the next even

numbered state (modulo 8). • If the e input is 0, the next state is the next odd numbered

state (modulo 8). • States are encoded using J-K flip-flops labeled X, Y & Z with

X the MSB. • The counter has no output other than the state flip-flops.

Give the state table, the state diagram and the minimized equations For the J and K inputs to each flip-flop.

X Y Z e X+ Y+ Z+ JX KX JY KY JZ KZ 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 13 Winter, 2017

PROBLEM #6, Continued:

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 14 Winter, 2017

PROBLEM #6, Continued: XY / Ze 0 0 0 1 1 1 1 0 XY / Ze 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

XY / Ze 0 0 0 1 1 1 1 0 XY / Ze 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

XY / Ze 0 0 0 1 1 1 1 0 XY / Ze 0 0 0 1 1 1 1 0

0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

ECE 204 Introduction to Digital Logic Bill Nelson Homework #7

03/012017 15 Winter, 2017

7. Draw a five D flip-flop PN counter using an XOR and taps at stages

3 and 5. Do not include forbidden state detection. Show the first 12 successive states assuming the initial state is {1,0,0,0,1}.