VHDL

Lab 3 Cover Sheet Name:

Adders and Two’s Complement Date:

Grade Item Grade

Attached block diagrams/schematics of (T1) Ripple-Carry Adder, (T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder using Two’s Complement: /9

VHDL Code showing the design of your (T1) Full Adder and Ripple-Carry Adder, (T2) Two’s Complement circuit, and (T3) Ripple-Carry Adder using Two’s Complement: /9

Simulation screenshots showing correct operation of your (T1) Ripple-Carry Adder and (T2) Two’s Complement circuit: /6

Demonstrations of VHDL code, simulation waveforms, and FPGA implementation of (T3) Ripple-Carry Adder using Two’s Complement: /5

Questions on cover sheet: /8

Total Grade: /37

VHDL Code:

Copy-paste your VHDL design module code for:

1. Your full adder and ripple-carry adder (task 1):

2. Your two’s complement circuit (task 2):

3. Your ripple-carry adder using two’s complement (task 3):

Simulation Screenshots:

Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program).

1. Your ripple-carry adder (task 1):

2. Your two’s complement circuit (task 2):

Simulation Screenshot Tips: (you can delete this once you capture your screenshot)

1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window

2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms

3. In order to not print a lot of black, change the color scheme of the “Wave” window:

3.1. Click Tools(Edit Preferences…

3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left

3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen.

3.4. Now color the waveforms and text black:

3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen.

3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print)

3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme

Questions: (Please use this cover sheet to type and print your responses)

1. Explain the design process that you used to create the RCA and Two’s Complement circuits (lab tasks 1 and 2). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL.

2. When adding two 4-bit numbers together, an addition overflow may occur and carry-out will be ‘1’. Why is this a problem if we are adding unsigned numbers? Why may this be beneficial if we are adding signed numbers (using two’s complement)?

3. Explain the design process that you used to create the 4-bit RCA using Two’s Complement (lab task 3). Be sure to refer to your schematics/block diagrams and the process to translate these into VHDL.

As a follow-up question, do you feel that your design is optimal (please explain)? Is there any way you could have better minimized your use of full adders and logic gates (please explain)?

4. Give two reasons why we may not want to create a test bench to simulate a circuit using all possible input signal combinations: