Digital Design and Computer Architecture homework
maxcaesar
hw2.pdf
ECE 314
Assignment
Due November 1 2016 at the start of class
1. A processor has a 32 MB cache and a 64 bit data bus. What is the minimum width of the
address bus needed to access the entire cache?
2. Explain why SRAM is less dense but faster than DRAM.
3. Give the machine code for the following assembly instructions (give your answer in hex
format):
beq $a0, $a1, L1 (the beq instruction is at address 0x00E20710 and the target L1 is at address
0x00E20724).
4. List the values on the control signals for the following instructions. The MIPS architecture and
instruction formats studied in class are shown below for reference. Your answer needs to be 1, 0,
or X for each signal (a 0 or 1 will not be accepted as a substitute for X).
MemtoReg MemWrite Branch ALUSrc RegDst RegWrite
sub r2, r5, r23
beq r1, r3, L2
sw r1, 36(r4)
lw r3,100(r6)
addi r2,r14,-24
j L3
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1 WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE 0
1
PC0
1
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg 4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl 2:0
A L
U
