VHDL project

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Final Project – Hardware Trojan Insertion

Lab Objectives

In this project, you will examine the behavior of a traffic light controller circuit, and then attack it with a hardware Trojan (i.e., time bomb). An additional sub-objective is to get more familiar with the Xilinx ISE environment.

Files

All the files (i.e., cover page, VHDL template files, reading material, etc.) are contained in a folder called “Final Project” which is available for download on TITANium. You must download these files prior to completing the following tasks.

Background

A Hardware Trojan (HT) is a malicious modification of the circuitry of an integrated circuit. A hardware Trojan is completely characterized by its physical representation and its behavior. The payload of an HT is the entire activity that the Trojan executes when it is triggered. In general, malicious Trojans try to bypass or disable the security fence of a system (e.g., it can leak confidential information by radio emission). HTs also could disable, derange or destroy the entire chip or components of it.

Work Task

Step 1 – Traffic Light Simulation

It is often useful to be able to sequence through an arbitrary number of states, staying in each state an arbitrary amount of time. For example, consider the set of traffic lights shown in Figure 1. The lights are assumed to be at a four-way intersection with one street going north-south and the other road going east-west. A state diagram for controlling these traffic lights is shown in Figure 2 and Table 1 shows the traffic light state. For this first step, complete the VHDL code that simulates the traffic light.

To simulate these traffic lights, you will create a Finite State Machine (FSM). A state diagram for controlling these traffic lights is shown in Figure 2. Table 1 below also shows how many clock cycles for each state and which lights to turn on. The three LSB of the “lights” output signal in the “traffic.vhd” are the green (bit 0), yellow (bit 1), and red (bit 2) lights of the north-south light. The three MSB are the green (bit 3), yellow (bit 4), and red (bit 5) lights of the east-west light (see Figure 3). The count variable in Figure 2 will be reset to zero when moving to the next state after a timeout. In the template, provide the code (“traffic.vhd” and “traffic_tb.vhd”) for this step. See “EGCP_447_FSM.pdf” for an example on how to code a FSM in VHDL.

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Figure 1: Traffic lights.

Figure 2: State diagram for controlling traffic lights.

Table 1: Traffic Light States

State North – South East – West Count

0 Green Red 15

1 Yellow Red 3

2 Red Red 3

3 Red Green 15

4 Red Yellow 3

5 Red Red 3

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Figure 3: Waveform of traffic light program (state is shown but is not necessary for your waveform).

Step 2 – Insert a Time Bomb

Now alter “traffic.vhd” from step 1 such that after the traffic lights cycles 4 times, a time bomb is set off that cause both north-south and east-west to show a green light indefinitely. A traffic light cycle is when the FSM has gone through all the states in Table 1 above (i.e., S0 to S5 and back to S0). In the template, also provide the code for this step.

What to Turn In (Please read this carefully)

For this project, you only need to provide the VHDL code and the answers for the “Work Task” section. You must put the complete VHDL code and the answers into a single PDF. Your code must be in text format. Code provided as an image will not be accepted. You must label everything appropriately (i.e., label the code and work task sections). If I can’t understand your answers or code, I will assume it is incorrect. Also, please include the cover page in your pdf document. This project will be a digital submission and it will be submitted online using TITANium. No paper submissions will be accepted.

VHDL project/traffic.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity traffic is port ( clk : in std_logic; clr : in std_logic; lights : out std_logic_vector(5 downto 0); cnt : out std_logic_vector(3 downto 0) ); end traffic; architecture traffic of traffic is -- These are some suggested signals that you can use -- Feel free to change or add to this type state_type is (s0, s1, s2, s3, s4, s5); signal state : state_type; signal count : std_logic_vector(3 downto 0); begin -- TO DO: enter code for FSM end traffic;