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Midterm 2 Solution/f14m2s_dild7.pdf

VHDL Design and Simulation f14m2s_dild7.fm - 1 Dr. Anthony D. Johnson

4/2/15

Digital Logic Design

Midterm #2

Problems Points

1. _____ 5

2. _____ 4

3. _____ 6

Total _____ 15

yes

Was the exam fair ?

VHDL Design and Simulation f14m2s_dild7.fm - 2 Dr. Anthony D. Johnson

4/2/15

Problem 1 5 points

Given is the logic model of a state machine shown in Figure 1.1.

Using the given logical model of Figure 1.1, demonstrate an ability to:

1. determine the expressions of logic functions at the outputs of all logic gates in the combinational block of the logical model;

2. apply the knowledge of Boolean algebra to simplification of logic functions; 3. recite the characteristic function of a JK-type flip-flop, and compose expressions of the

state transition exitacion functions of the internal memory block; 4. derive the content of the State Transition Table from the Next State Functions, 5. draw the State Transition Graph based on a prepared State Transition Table.

Hint #1 For full credit: all equations, all answers to questions, all circuit models and other graphical representations are expected to be entered into the space designated for them; all shown numerical results must be preceded by the symbolic and numeric expressions whose evaluation produces the results.

Solution An explicit demonstration of understanding the following solution steps is expected.

1.1 Next to the outputs of logic gates in the circuit of Figure 1.1(a), indicate the expressions of logic gates’ output functions. Write in the space reserved for Figure 1.1(b) the expressions of the excitation functions of internal memory flip-flops and the expression of the output function

Figure 1.1 A state machine with two flip-flops in its internal state memory block. (a)Logical model of the circuit. (b)Derived excitation functions of the internal state memory flip-flops and the output function z.

(a)

(b) J1 = (y1+A)y2 J2 = y1(y1+y2) Z = Ay1y2

K Q

CLK

y1+A

y1+y2 y1(y1+y2)

(y1+A)y2 A FF1

FF2

K Q

K1 = K2 = A

0.5

VHDL Design and Simulation f14m2s_dild7.fm - 3 Dr. Anthony D. Johnson

4/2/15

1.2 In the space reserved for equation (1-1) fill in the expression of the JK-type flip-flop’s characteristic function.

1.3 In the space reserved for equations (1-2) through (1-6), fill in the simplified expressions of the flip-flop exitation functions of the internal state memory (flip-flops), and the output Z.

1.4 In the space reserved for equations (1-7) and (1-8), fill in the simplified expressions of the state transition functions of the internal state memory flip-flops.

1.5 In the space reserved for Figure 1.2(a), fill in the contents of the State transition table of the sequential circuit model of Figure 1.1.

1.6 In the space reserved for Figure 1.2(b), prepare the drawing of the State transition graph (state diagram) of the sequential logical circuit of Figure 1.1.

0.5

Y i = Ji⋅yi + Ki⋅yi (1-1)

J1= (A+y1)y2 (1-4)

(1-5)

Z = A⋅y1⋅y2 (1-6)

K1= A K2= A

(1-2)

(1-3)

J2 = y1(y1+y2) = y1y2

Y1= J1⋅y1+K1⋅y1= (A+y1)⋅y2⋅y1+A⋅y1 = A⋅y1⋅y2+y1⋅y2+A⋅y1 = A⋅y1 + y1⋅y2

Y2= J2⋅y2 + K2⋅y2 = y1⋅y2⋅y2 + A⋅y2 = A⋅y2

(1-7)

(1-8)

11/0 10/0

10/0 00/0

11/0 00/1

Figure 1.2 Results of the analysis. (a)State transition table of the SM from Figure 1.1(a). (b)State transition graph (State diagram) of the SM from Figure 1.1(a).

(a)

0 1 A

y1y2

00/0 00/0

(b)

Y1Y2/z 10

1/1 1/0

0,1/0

1/0

0/0

VHDL Design and Simulation f14m2s_dild7.fm - 4 Dr. Anthony D. Johnson

4/2/15

Problem 2 4 points

Given is a logic function F2 in the decimal sum of minterms representation (2-1).

F(A,B,C,D) = Σ( 1, 2, 6, 7, 8, 9, 12, 15) (2-1)

For the logic function (2-1), demonstrate an ability to: 1. design a combinational cicuit which uses an 8:1 multiplexer module to implement the

function (2-1), 2. apply the design method which is based on preparation of either one of the following

two tables: - MUX Implementation Table, or - Truth Table of the function to be implemented.

Solution An explicit demonstration of understanding the following solution steps is expected.

2.1 Depending on the selected design method, fill in the missing data in either the MUX Implementation Table of Figure 2.1(a), or the Truth Table of Figure 2.2(a).

2.2 Consistent with the selected design method, show in the space reserved for Figure 2.1(b), or

0 1 2 3 4 5 6 7

I0 I1 I2 I3 I4 I5 I6 I7

8 9 10 11 12 13 14 15

A 1 A 0 A 0 A 1

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

B C D

A 1

(b)(a)

Figure 2.1 MUX Implementation Table method. (a)MUX implementation table. (b)Implementation of the function (2-1).

VHDL Design and Simulation f14m2s_dild7.fm - 5 Dr. Anthony D. Johnson

4/2/15

alternatively in the space reserved for Figure 2.2(b), how the logic constants 0 and 1, and the literals of the logic variables A, B, C, and D ought to be applied to the inputs of the MUX module.

(a)

Figure 2.2 TruthTable method. (a)Truth table. (b)Implementation of the function (2-1).

(b)

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

A B C

0 1 1 0 D D

A B C F

D k=(ABC)2

VHDL Design and Simulation f14m2s_dild7.fm - 6 Dr. Anthony D. Johnson

4/2/15

Problem 3 6 points

Given is the following verbal specification of a state machine (SM): (a) the SM has one signal input A, (b) the SM has one signal output Z, (c) the SM recognizes the input bit sequence 101. (d) every time the input sequence 101 has been recognized, the output signal Z is set to Z

=1, otherwise Z =0, (e) the SM is to be implemented using the positive-edge triggered D-type flip flop(s),

Based on the given specification, demonstrate an ability to: 1. compose the graphical representation of the State Transition Graph of a state machine

that will implement the given verbal specification of the SM, 2. compose a StateTransition Table which describes the same State Machine as already

described by the composed State Transition Graph, 3. combine the information from the State Transition Table ad the D-type flip-flop’s

Excitation Table to prepare the Transition Excitation Table of the specified SM. 4. apply the Karnaugh Map simplification method to derive the internal state excitation

functions described in the Transition Excitation Table of the specified SM, 5. compose a minimum number of logic gates circuit which implements the State Machine

for which the internal state memory is specified, and for which the flip-flop excitation functions have been known.

Solution

An explicit demonstration of understanding the following solution steps is expected.

3.1 In the space reserved for Figure 3.2(a) prepare a graphical representation of the State Transition Graph of the SM that will implement the given verbal specification.

3.2 In the space reserved for Figure 3.2(b) fill in the contents of the State Transition Table that corresponds to the prepared state transition graph.

3.3 In the space reserved for Figure 3.2(c) fill in the contents of the Excitation Table of a D-type flip-flop.

Figure 3.1 General architecture of a Mealy type State Machine.

/sA Z

Clock

/ s

Internal state

memory

Y yN Q I

I Output logic

Next state logic

VHDL Design and Simulation f14m2s_dild7.fm - 7 Dr. Anthony D. Johnson

4/2/15

3.4 In the space reserved for Figure 3.2(d), compose the State Transition Excitation Table of the SM by combining the information from the state transition table of the SM and the excitation table of the flip-flop.

3.5 Using the Karnaugh map method, derive the simplified expressions of the flip-flop excitation function(s) D and the output function Z, and manipulate these expressions into the minimum number of literals form. Enter the obtained minimum number of literals expresions of the functions D and Z in the space reserved for Figure 3.2(e).

Figure 4.2 State Machine design process. (a) State transition graph of the SM. (b)State transition table of the SM. (c)D-type flip-flop excitation table. (d)State transition excitation table of the SM. (e)Karnaugh maps, and minimum number of literals expressions of logic functions D1, D2, and Z.

(a)

(c)

D1 = Ay2

(e)

(d)

Z = Ay1y2

0 0

1 0

0 1

Y1 D1 Z

0 1

0 0

00 01 10 11 y1y2

A 0

1 01/0 01/101/0 d 00/0 00/010/0 d

Y1Y2/Z

1 0

Q+

0 1

0 0

10Ay1 y2

1Ay1 y2

1 d

10Ay1 y2

Z - Kmap

D2 = A

D1 - Kmap

11 0/0

0/0

1/1

0/0

1/0

(b)

D2 - Kmap

? 1 10 101

Sequence Received

1/0

States 01 and 11 are equivalent

Sequences 1 and 101 are equivalent WRT

because:

the start of next one.

VHDL Design and Simulation f14m2s_dild7.fm - 8 Dr. Anthony D. Johnson

4/2/15

3.6 In the space reserved for Figure 3.3 prepare the minimum number of gates logic circuit model which implements the State Machine whose specification is given at the beginning of this problem.

Figure 3.3 Logic circuit model of the State Machine that implements the recognizer of bit sequence 101.

Q D y2

CLK

Ay2

Z=Ay1y2

y2 FF1

FF2

Q D y1

A Y2

Midterm 2 Solution/f15m2s_dild7.pdf

f15m2s_dild7.fm - 1 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Digital Logic Design

Midterm #2

Problems Points

1. _____ 5

2. _____ 4

3. _____ 6

Total _____ 15

yes

Was the exam fair ?

f15m2s_dild7.fm - 2 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 1 5 points

Given is the logic circuit model of a state machine shown in Figure 1.1.

Problem Statement Using the given logical model of Figure 1.1, demonstrate an ability to:

1. determine the expressions of logic functions at the outputs of all logic gates in the combinational block of the logical model;

2. apply the knowledge of Boolean algebra to simplification of logic functions; 3. recite the characteristic function of a D-type flip-flop, and compose expressions of the next

state functions of the internal memory block; 4. derive the content of the State Transition Table from the Next State Functions, 5. draw the State Transition Graph based on a prepared State Transition Table.

Figure 1.1 A state machine with two flip-flops in its internal state memory block. (a)Logic model of the circuit. (b)Derived excitation functions of the internal state memory flip-flops and the output function z.

(a)

(b)

Y1 = y2(A+y1) Y2 = y1(A+y2) Z = y1y2

CLK

y2y2

Q D

FF1

FF2

y2(A+y1)A+y1

A+y2 y1(A+y2)

f15m2s_dild7.fm - 3 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

1.2 In the space reserved for equation (1-1) fill in the expression of the D-type flip-flop’s characteristic function.

1.3 In the space reserved for equations (1-2) and (1-3), fill in the simplified expressions of the next state functions of the internal state memory (flip-flops).

1.4 In the space reserved for Figure 1.2(a), fill in the contents of the State transition table of the sequential circuit model of Figure 1.1.

1.5 In the space reserved for Figure 1.2(b), prepare the drawing of the State transition graph (state diagram) of the sequential logic circuit of Figure 1.1.

Q+= D (1-1)

Y1= D1⋅= y2(A+y1)

Y2= D2= y1(A+y2)

(1-2)

(1-3)

Z = y1y2 (1-4)

Figure 1.2 Results of the analysis. (a)State transition table of the SM from Figure 1.1(a). (b)State transition graph (State diagram) of the SM from Figure 1.1(a).

(a) (b)

11/1 11/1

00/0 00/0

00/0 10/0

0 1A y1y2

00/0 01/0

Y1Y2/z 10

1/0

0/0

0,1/0

0,1/1 01

0/0

1/0

f15m2s_dild7.fm - 4 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 2 4 points

Given is a logic function F2 in the decimal sum of minterms representation (2-1).

Problem Statement For the logic function (2-1), demonstrate an ability to:

1. design a combinational circuit which uses an 8:1 multiplexer module to implement the function (2-1),

2. apply the design method which is based on preparation of either one of the following two tables:

- MUX Implementation Table, or

- Truth Table of the function to be implemented. Hint #1 For full credit: all equations, all answers to questions, all circuit models and other

graphical representations are expected to be entered into the space designated for them; all shown numerical results must be preceded by the symbolic and numeric expressions whose evaluation produces the shown results.

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

2.1 Depending on the selected design method, fill in the missing data in either the MUX Implementation Table of Figure 2.1(a), or the Truth Table of Figure 2.2(a).

2.2 Consistent with the selected design method, show in the space reserved for Figure 2.1(b), or

(2-1)F2(A,B,C,D) = Σ( 0, 2, 4, 5, 8, 9, 10, 12, 14)

0 1 2 3 4 5 6 7

I0 I1 I2 I3 I4 I5 I6 I7

8 9 10 11 12 13 14 15

1 A 1 0 1 A A 0

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

B C D

A 0

(b)

(a)

Figure 2.1 MUX Implementation Table method. (a)MUX implementation table. (b)Implementation of the function (2-1).

f15m2s_dild7.fm - 5 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

alternatively in the space reserved for Figure 2.2(b), how the logical constants 0 and 1, and the literals of the logical variables A, B, C, and D ought to be applied to the MUX module’s inputs.

An Alternative Problem Solution

(a)

Figure 2.2 Truth Table method. (a)Truth table. (b)Implementation of the function (2-1).

(b)

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

A B C

1 D

D D

A B C F

D k=(s2s1s0)2

f15m2s_dild7.fm - 6 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 3 6 points

Given is the following verbal specification of a state machine (SM): (a) the SM has one input signal S, (b) the SM has one output signal output Z, (c) the SM recognizes the input signal sequence 100, (d) every time the input signal sequence 100 has been observed by the SM, the output signal

Z is set to Z =1, otherwise Z =0; (overlapping sequences recognized). (e) the SM is to be implemented using positive edge triggered D-type flip-flop(s).

Problem Statement Based on the given specification, demonstrate an ability to:

1. compose the graphical representation of the State Transition Graph of a state machine that will implement the given verbal specification of the SM,

2. compose a State Transition Table which describes the same State Machine as already described by the composed State Transition Graph,

3. combine the information from the State Transition Table ad the flip-flop’s Excitation Table to prepare the Transition Excitation Table of the specified SM.

4. apply the Karnaugh Map simplification method to derive the internal state excitation functions described in the Transition Excitation Table of the specified SM,

5. compose a minimum number of logic gates circuit which implements the State Machine for which the internal state memory is specified, and for which the flip-flop excitation functions have been derived.

Figure 3.1 General architecture of a Mealy type State Machine.

/nS Z

CLK

Internal state

memory

Y yN Q I

I Output

logic

Next state logic

f15m2s_dild7.fm - 7 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

3.1 Assigning to the initial state the binary encoded name "00", prepare a graphical representation of the State Transition Graph of the SM which will implement the given verbal specification. Show the prepared State Transition graph in the space reserved for Figure 3.2(a).

3.2 In the space reserved for Figure 3.2(b) fill in the contents of the State Transition Table that corresponds to the prepared state transition graph.

3.3 In the space reserved for Figure 3.2(c) fill in the contents of the Excitation Table of a D-type flip-flop.

3.5 Using the Karnaugh map method, derive the simplified expressions of the flip-flop excitation function(s) D1, D2 and the output function Z, and manipulate them into expressions with minimum number of literals. Show the obtained expressions into the space reserved for Figure 3.2(f).

Figure 3.2 Design process of the State Machine. (a)State transition graph of the SM. (b)State transition table of the SM. (c)D-type flip-flop excitation table. (d)State Transition excitation table of the SM. (e)Karnaugh maps of functions D1, D2 and Z. (f)Simplified expressions of logic functions D1, D2 and Z.

11 0/1

0/0

1/0

0/0

1/0

(b)

1/0

0 0

1 0

0 1

Y1 D1 Z

0 1

1 0

0 0

D2y

1 0

0 1

D1 = Sy2

(f) (e)

10Sy1 y2

Z-KmapD1-Kmap

10Sy1 y2

1 d

D2-Kmap

D2 = S

(a) (d)

Z = Sy1y2

0 1

0 0

0 1

0 0

00 01 10 11 y1y2

S 0

1 01/0 01/001/0 dd/0 00/0 00/110/0 dd/0

Y1Y2/Z

? 1 10 100

f15m2s_dild7.fm - 8 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

3.6 In the space reserved for Figure 3.3 prepare the minimum number of logic gates logical circuit model which implements the State Machine whose specification is given at the beginning of this problem.1

Figure 3.3 Logical circuit model of the State Machine that implements the sequence recognizer for sequence 011.

CLK

Z = Sy1y2

Q D

CLK

Q D

CLK

FF1

FF2

Midterm 2 Solution/s14m2s_dild7.pdf

s14m2s_dild7.fm - 1 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Digital Logic Design

Midterm #2

Problems Points

1. _____ 5

2. _____ 4

3. _____ 6

Total _____ 15

yes

Was the exam fair ?

s14m2s_dild7.fm - 2 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 1 5 points

Given is the logical model of a state machine as shown in Figure 1.1.

Using the given logical model of Figure 1.1, demonstrate an ability to: 1. determine the expressions of logic functions at the outputs of all logic gates in the

combinational block of the logical model; 2. apply the knowledge of Boolean algebra to simplification of logic functions; 3. recite the characteristic function of a D-type flip-flop, and compose expressions of the next

Solution An explicit demonstration of understanding the following solution steps is expected.

(a)

(b)

Y1 = (y1+A)y2 Y2 = y1(y1+y2)

CLK

Q D

y1+A

y1+y2 y1(y1+y2)

(y1+A)y2 A

FF1

FF2

Z = Ay1y2

s14m2s_dild7.fm - 3 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

excitation functions of internal memory flip-flops and the expression of the output function Z.

1.2 In the space reserved for equation (1-1) fill in the expression of the D-type flip-flop’s characteristic function.

Q+= D (1-1)

1.3 In the space reserved for equations (1-2) and (1-3), fill in the simplified expressions of the next state functions of the internal state memory (flip-flops).

1.4 In the space reserved for Figure 1.2(a), fill in the contents of the State transition table of the sequential circuit model of Figure 1.1.

1.5 In the space reserved for Figure 1.2(b), prepare the drawing of the State transition graph (state diagram) of the sequential logical circuit of Figure 1.1.

Y1= D1⋅= (y1+A)y2

Y2= D2= y1(y1+y2) = y1y2

(1-2)

(1-3)

Z = A⋅y1⋅y2 (1-4)

11/0 11/0

00/0 00/0

00/0 10/1

Figure 1.2 Results of the analysis. (a)State transition table of the SM from Figure 1.1(a). (b)State transition graph (State diagram) of the SM from Figure 1.1(a).

(a)

0 1 A

y1y2

00/0 00/0

(b)

Y1Y2/z 10

1/1

0/0

0,1/0

0,1/0 01

0,1/0

s14m2s_dild7.fm - 4 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 2 4 points

Given is a logic function F2 in the decimal sum of minterms representation (2-1).

F(A,B,C,D) = Σ( 0, 2, 5, 7, 8, 12, 13, 14) (2-1)

For the logic function (2-1), demonstrate an ability to: 1. design a combinational cicuit which uses an 8:1 multiplexer module to implement the

function (2-1), 2. apply the design method which is based on preparation of either one of the following two

tables: - MUX Implementation Table, or

- Truth Table of the function to be implemented. Hint #1 For full credit: all equations, all answers to questions, all circuit models and other

Solution An explicit demonstration of understanding the following solution steps is expected.

2.1 Depending on the selected design method, fill in the missing data in either the MUX Implementation Table of Figure 2.1(a), or the Truth Table of Figure 2.2(a).

2.2 Consistent with the selected design method, show in the space reserved for Figure 2.1(b), or

0 1 2 3 4 5 6 7

I0 I1 I2 I3 I4 I5 I6 I7

8 9 10 11 12 13 14 15

1 0 A 0 A 1 A A

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

B C D

A A

(b)(a)

Figure 2.1 MUX Implementation Table method. (a)MUX implementation table. (b)Implementation of the function (2-1).

s14m2s_dild7.fm - 5 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

alternatively in the space reserved for Figure 2.2(b), how the logical constants 0 and 1, and the literals of the logical variables A, B, C, and D ought to be applied to the inputs of the MUX module.

(a)

Figure 2.2 TruthTable method. (a)Truth table. (b)Implementation of the function (2-1).

(b)

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

A B C

D 0

1 D

A B C F

D k=(s2s1s0)2

s14m2s_dild7.fm - 6 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 3 6 points

Given is the following verbal specification of a state machine (SM): (a) the SM has one signal input A, (b) the SM has one signal output Z, (c) the SM recognizes the input signal sequence 10. (d) every time the input signal sequence 10 has been recognized, the output signal Z is set to

Z =1, otherwise Z =0, (e) the SM is to be implemented using positive edge triggered D-type flip flop(s),

Based on the given specification, demonstrate an ability to: 1. compose the graphical representation of the State Transition Graph of a state machine that

will implement the given verbal specification of the SM, 2. compose a StateTransition Table which describes the same State Machine as already

described by the composed State Transition Graph, 3. combine the information from the State Transition Table ad the D-type flip-flop’s

Excitation Table to prepare the Transition Excitation Table of the specified SM. 4. apply the Karnaugh Map simplification method to derive the internal state excitation

functions described in the Transition Excitation Table of the specified SM, 5. compose a minimum number of logic gates circuit which implements the State Machine

for which the internal state memory is specified, and for which the flip-flop excitation functions have been derived.

Figure 3.1 General architecture of a Mealy type State Machine.

/sA Z

Clock

/ s

Internal state

memory

Y yN Q I

I Output logic

Next state logic

s14m2s_dild7.fm - 7 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Solution An explicit demonstration of understanding the following solution steps is expected.

3.1 In the space reserved for Figure 3.2(a) prepare a graphical representation of the State Transition Graph of the SM that will implement the given verbal specification.

3.2 In the space reserved for Figure 3.2(b) fill in the contents of the State Transition Table that corresponds to the prepared state transition graph.

3.3 In the space reserved for Figure 3.2(c) fill in the contents of the Excitation Table of a D-type flip-flop.

(e) (f)(d)

D = A

D- Kmap

(a)

Figure 3.2 Design process of the State Machine. (a) State transition graph of the SM. (b) State transition table of the SM. (b)D-type flip-flop excitation table. (c)Transition excitation table of the SM. (d)Karnaugh maps of the functions D and Z. (e) Simplified expressions of the logic functions D and Z.

0/1 1/0

0 1 A

0/0 1/0

Y/Z

Z = yA

Z- Kmap

1 0

0 1

D Z

0 1

1 0

Q+

0 1

(b)

1/0 1/0

0/1

0/0

(c)

A y

s14m2s_dild7.fm - 8 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Figure 3.3 Logical circuit model of the State Machine that implements the recognizer of the input sequence 10.

CLK Q

Q D y

Midterm 2 Solution/s15m2s_dild7.pdf

s15m2s_dild7.fm - 1 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Digital Logic Design

Midterm #2

Problems Points

1. _____ 5

2. _____ 4

3. _____ 6

Total _____ 15

yes

Was the exam fair ?

s15m2s_dild7.fm - 2 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 1 5 points

Given is the logic circuit model of a state machine shown in Figure 1.1.

Problem Statement Using the given logical model of Figure 1.1, demonstrate an ability to:

1. determine the expressions of logic functions at the outputs of all logic gates in the combinational block of the logical model;

2. apply the knowledge of Boolean algebra to simplification of logic functions; 3. recite the characteristic function of a D-type flip-flop, and compose expressions of the next

(a)

(b)

Y1 = Ay1y2 Y2 = y1y2 = y1+y2

CLK

Q D

Ay1

y1+y2 y1+y2

Ay1y2 A

FF1

FF2

Z = Ay1y2

s15m2s_dild7.fm - 3 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

1.2 In the space reserved for equation (1-1) fill in the expression of the D-type flip-flop’s characteristic function.

Q+= D (1-1)

1.3 In the space reserved for equations (1-2) and (1-3), fill in the simplified expressions of the next state functions of the internal state memory (flip-flops).

1.4 In the space reserved for Figure 1.2(a), fill in the contents of the State transition table of the sequential circuit model of Figure 1.1.

1.5 In the space reserved for Figure 1.2(b), prepare the drawing of the State transition graph (state diagram) of the sequential logical circuit of Figure 1.1.

Y1= D1⋅= Ay1y2

Y2= D2= y1+y2

(1-2)

(1-3)

Z = A⋅y1⋅y2 (1-4)

00/0 00/0

01/0 01/0

11/0 01/1

Figure 1.2 Results of the analysis. (a)State transition table of the SM from Figure 1.1(a). (b)State transition graph (State diagram) of the SM from Figure 1.1(a).

(a)

0 1 A

y1y2

01/0 01/0

(b)

Y1Y2/z 10

0,1/0

1/1 01

0/0

0, 1/

00, 1/

s15m2s_dild7.fm - 4 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 2 4 points

Given is a logic function F2 in the decimal sum of minterms representation (2-1).

F(A,B,C,D) = Σ( 1, 2, 3, 4, 6, 10, 12, 13, 15) (2-1)

Problem Statement For the logic function (2-1), demonstrate an ability to:

1. design a combinational circuit which uses an 8:1 multiplexer module to implement the function (2-1),

2. apply the design method which is based on preparation of either one of the following two tables:

- MUX Implementation Table, or

- Truth Table of the function to be implemented. Hint #1 For full credit: all equations, all answers to questions, all circuit models and other

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

2.1 Depending on the selected design method, fill in the missing data in either the MUX Implementation Table of Figure 2.1(a), or the Truth Table of Figure 2.2(a).

2.2 Consistent with the selected design method, show in the space reserved for Figure 2.1(b), or alternatively in the space reserved for Figure 2.2(b), how the logical constants 0 and 1, and the literals of the logical variables A, B, C, and D ought to be applied to the MUX module’s inputs.

0 1 2 3 4 5 6 7

I0 I1 I2 I3 I4 I5 I6 I7

8 9 10 11 12 13 14 15

0 A 1 A 1 A A A

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

B C D

A A

(b)

(a)

Figure 2.1 MUX Implementation Table method. (a)MUX implementation table. (b)Implementation of the function (2-1).

s15m2s_dild7.fm - 5 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

An Alternative Problem Solution

(a)

Figure 2.2 TruthTable method. (a)Truth table. (b)Implementation of the function (2-1).

(b)

7 s2 s1 s0

MUX 8:1

F(A,B,C,D)

A B C

0 D

A B C F

D k=(s2s1s0)2

s15m2s_dild7.fm - 6 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem 3 6 points

Given is the following verbal specification of a state machine (SM): (a) the SM has one input signal S, (b) the SM has one output signal output Z, (c) the SM recognizes the input signal sequence 011, (d) every time the input signal sequence 011 has been recognized, the output signal Z is set to

Z =1, otherwise Z =0, (e) the SM is to be implemented using positive edge triggered JK-type flip-flop(s).

Problem Statement Based on the given specification, demonstrate an ability to:

1. compose the graphical representation of the State Transition Graph of a state machine that will implement the given verbal specification of the SM,

2. compose a State Transition Table which describes the same State Machine as already described by the composed State Transition Graph,

3. combine the information from the State Transition Table ad the flip-flop’s Excitation Table to prepare the Transition Excitation Table of the specified SM.

4. apply the Karnaugh Map simplification method to derive the internal state excitation functions described in the Transition Excitation Table of the specified SM,

Figure 3.1 General architecture of a Mealy type State Machine.

/nS Z

CLK

/ n

Internal state

memory

Y yN Q I

I Output logic

Next state logic

s15m2s_dild7.fm - 7 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

Problem Solution An explicit demonstration of understanding the following solution steps is expected.

3.2 In the space reserved for Figure 3.2(b) fill in the contents of the State Transition Table that corresponds to the prepared state transition graph.

3.3 In the space reserved for Figure 3.2(c) fill in the contents of the Excitation Table of a JK-type flip-flop.

3.5 Using the Karnaugh map method, derive the simplified expressions of the flip-flop excitation function(s) J1, K1, J2, K2 and the output function Z, and manipulate these expressions into the minimum number of literals form. Enter the obtained minimum number of literals expressions of

s15m2s_dild7.fm - 8 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________

the functions J1, K1, J2, K2 and Z and Z in the space reserved for Figure 3.2(f).

Figure 3.2 Design process of the State Machine. (a) State transition graph of the SM. (b) State transition table of the SM. (b)JK-type flip-flop excitation table. (c)Transition excitation table of the SM. (d)Karnaugh maps of the functions J1, K1, J2, K2 and Z. (e) Simplified expressions of logic functions J1, K1, J2, K2 and Z.

11 1/1

1/0

0/0

1/0

0/0

(b)

0/0

(c)

0 0

1 0

0 1

Y1 J1 Z

0 0

d 0

0 0

1 1

1 d

d 0

1 0

0 1

d 1

1 d

J1 = Sy2

(f)(e)

10Sy1 y2

d d

1Sy1 y2

1 d

10Sy1 y2

Z- Kmap

K1 = 1

J1- Kmap K1- Kmap

10Sy1 y2

1Sy1 y2

d d

J2- Kmap K2- Kmap

J2 = S

K2 = S

(a)

(d)

Z = Sy1y2

00 01 10 11 y1y2

S 0

1 00/0 00/110/0 dd/0 01/0 01/001/0 dd/0

Y1Y2/Z

? 0 01 011

Figure 3.3 Logical circuit model of the State Machine that implements the recognizer of the input sequence 011.

CLK

Sy2

Z=Sy1y2

K Q

FF1

K Q

FF2

s15m2s_dild7.fm - 9 The University of Toledo Section ________ EECS:1100 Digital Logic Design Dr. Anthony D. Johnson Student Name ___________________________