VHDL CODE for RAM Implementation of Hack Computer

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity tdp_ram is

generic (

DATA : integer := 32;

ADDR : integer := 10

);

port (

-- Port A

rw_clock : in std_logic;

rw_load : in std_logic;

rw_address : in std_logic_vector(ADDR-1 downto 0);

rw_data : in std_logic_vector(DATA-1 downto 0);

rw_out : out std_logic_vector(DATA-1 downto 0);

-- Port B

ro_clock : in std_logic;

ro_load : in std_logic;

ro_address : in std_logic_vector(ADDR-1 downto 0);

ro_data : in std_logic_vector(DATA-1 downto 0);

ro_out : out std_logic_vector(DATA-1 downto 0)

);

end tdp_ram;

architecture rtl of tdp_ram is

-- Shared memory

type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0);

shared variable mem : mem_type;

begin

-- Port A

process(rw_clock)

begin

if(rw_clock = '1') then

if(rw_load='1') then

mem(conv_integer(rw_address)) := rw_data;

end if;

rw_out <= mem(conv_integer(rw_address));

end if;

end process;

-- Port B

process(ro_clock)

begin

if(ro_clock = '1') then

if(ro_load='1') then

mem(conv_integer(ro_address)) := ro_data;

end if;

ro_out <= mem(conv_integer(ro_address));

end if;

end process;

end rtl;