VHDL RAM and Quartus 2 University Waveform Editor/Simulator Output Verification
debmouti190c
ram_vwf_ss.docxHere is my code. It does compile successfully.
-- =====================================================================
-- Author : Robert Weymouth
-- Title : TDP_RAM
-- Design : DATA Memory
-- SIZE : 16384 X 16 = 32 KB
-- Description : True Dual Port Memory unit
-- =====================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity TDPRAM is
generic (
DATA : integer := 15;
ADDR : integer := 13
);
Port (
-- Read & Write Port SIGNALS
rw_clock : in std_logic;
-- 14-address bit are required to access 16K Locations
rw_address : in STD_LOGIC_VECTOR (ADDR - 1 downto 0);
rw_data : in STD_LOGIC_VECTOR (DATA - 1 downto 0);
rw_load : in STD_LOGIC;
rw_out : out STD_LOGIC_VECTOR (DATA - 1 downto 0);
-- VGA Controller Port SIGNALS
ro_clock : in std_logic;
ro_address : in STD_LOGIC_VECTOR (ADDR - 1 downto 0);
ro_out : out STD_LOGIC_VECTOR (DATA - 1 downto 0));
end TDPRAM;
architecture Behavioral of TDPRAM is
type datamem is array (0 to 16383) of std_logic_vector (DATA - 1 downto 0);
-- Internal Signals for VGA Controller
signal ro_data :std_logic_vector(DATA - 1 downto 0):=(others=>'1');
signal ro_load :std_logic:='0';
signal RAM: datamem := (others =>(others=>'0'));
signal RAM1: datamem:= (others =>(others=>'0'));
begin
--Read & Write Port
Writing:
process(rw_clock,rw_address,rw_load,rw_data)
begin
if(rw_clock'event and rw_clock='1') then
if(rw_load='1') then
RAM(conv_integer(unsigned(rw_address)))<= rw_data;
end if;
end if;
end process;
Reading:
process (rw_clock,rw_address)
begin
if(rw_clock'event and rw_clock='1') then
if(rw_load='0') then
rw_out<= RAM(conv_integer(unsigned(rw_address)));
end if;
end if;
end process;
--VGA Controller Port
Writing1:
process(ro_clock,ro_address,ro_load,ro_data)
begin
if(ro_clock'event and ro_clock='1') then
if(ro_load='1') then
RAM1(conv_integer(unsigned(ro_address)))<= ro_data;
end if;
end if;
end process;
Reading1:
process (ro_clock,ro_address,ro_load)
begin
if(ro_clock'event and ro_clock='1') then
if(ro_load='0') then
ro_out<= RAM1(conv_integer(unsigned(ro_address)));
end if;
end if;
end process;
end Behavioral;
I am trying to test the code with the Quartus 2 waveform simulator below.
Here I set up my address, data, and load inputs.
Here I created my waveforms.
But my outputs are always zero? What am I doing wrong?
