VHDL code homework

Question no. 1 Write VHDL code for the LFSR circuit given in Fig 1. Use the

sample entity statement shown in Fig 2. Use the testbench code given with

assignment to test your VHDL code. (Note: For the D-flip-flop, make output node,

Q goes to logic ‘1’ or “high” when reset is at logic “1” or “high” and also if the name of the ports in the entity is different than the VHDL code shown in Fig 2, the

testbench will not work).

Fig 1 4-bit LFSR circuit

Fig 2 VHDL entity for the LFSR circuit

Question no. 2 For the given state machine shown in Fig 3 write the VHDL code. Use

the sample entity statement given in the question. Use the testbench code given with

assignment to test your VHDL code. (Note: if the name of the ports in the entity is

different than the VHDL code shown in Fig 4, the testbench will not work)

Fig 3 State machine

Fig 4 VHDL entity for the state machine

VHDL/LFSR_TB.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:00:15 09/10/2016 -- Design Name: -- Module Name: C:/Users/rkmah/Google Drive/EGCP 447/VHDL Demo/demo/LFSR_TB.vhd -- Project Name: demo -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: LFSR -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY LFSR_TB IS END LFSR_TB; ARCHITECTURE behavior OF LFSR_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT LFSR PORT( Clk : IN std_logic; Reset : IN std_logic; LFSR_out : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal Clk : std_logic := '0'; signal Reset : std_logic := '0'; --Outputs signal LFSR_out : std_logic_vector(3 downto 0); -- Clock period definitions constant Clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: LFSR PORT MAP ( Clk => Clk, Reset => Reset, LFSR_out => LFSR_out ); -- Clock process definitions Clk_process :process begin Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process; -- Resegt process definitions Re_set_process: process begin Reset <= '1'; wait for Clk_period *10; Reset <= '0'; wait for Clk_period *320; end process; END;