W5 Digital Electronics Multisim and VDHL Lab
danmelvanderson_i01c
vdhl_files.zipprob_c5_7.bdf
LIBRARY ieee; --Using VHDL to Simplify Equations USE ieee.std_logic_1164.ALL; ENTITY ex5_6 IS PORT( a,b,c :IN Std_logic; y, z :OUT Std_logic); END ex5_6; ARCHITECTURE arc ex5_6 IS BEGIN y<=(a NOR c) OR (b NAND c); z<=NOT ((a OR NOT c) OR (b AND c)); END arc;
prob_c5_6.bdf
LIBRARY ieee; --Using VHDL to Simplify Equations USE ieee.std_logic_1164.ALL; ENTITY ex5_6 IS PORT( a,b,c :IN Std_logic; x, y :OUT Std_logic); END ex5_6; ARCHITECTURE arc ex5_6 IS BEGIN x<=(b AND c) AND ((b OR (NOT a AND (b AND c)) OR (a AND b)); y<=a AND ((NOT c AND(a AND b) OR (b NAND c)); END arc;
prob_c5_5.bdf
LIBRARY ieee; --Using VHDL to Simplify Equations USE ieee.std_logic_1164.ALL; ENTITY ex5_5 IS PORT( a,b,c :IN Std_logic; x, y :OUT Std_logic); END ex5_5; ARCHITECTURE arc ex5_5 IS BEGIN x<=(NOT a AND b) AND (b OR (NOT b AND (NOT b AND C))); END arc;
