W6 Digital Electronics Multisim and VDHL Lab

prob_c7_1.vhdl

LIBRARY ieee; USE ieee.std_logic_1164.ALL; --Full Adder ENTITY exp7_1 IS PORT( a1 : IN std_logic; b1 : IN std_logic; cin : IN std_logic; sum1 : OUT std_logic; cout : OUT std_logic; ); END exp7_1; ARCHITECTURE arc OF exp7_1 BEGIN cout<=((a1 AND b1) OR (a1 AND cin) OR (b1 AND cin)) OR ((a1 XOR b1) XOR cin); sum<=(a1 XOR b1) XOR cin; END arc;