lab
allawy7
lab7_j-kflip-flop2.pdf
Lab 7 – The JK FF 1
Lab 7 J-K FF Objectives The following are objectives of this lab:
Use various conditions to test the characteristics of the J-K flip-flop. Included in the procedures are various asynchronous and synchronous input modes.
Materials Needed
1. 74LS76 dual J-K flip-flop 2. LEDs: (1) red, (1) green, (1) yellow 3. Resistors: (3) 330Ω, (4) 1.0 kΩ 4. One 4-position DIP switch 5. Function Generator / Oscilloscope / Leads / KeySight BenchVue software
Background The J-K flip-flop is a clocked S-R flip-flop with additional circuitry to replace the invalid state of S = 1, R = 1. The new mode when J = 1 and K = 1 is called toggle. The toggle state causes the flip- flop to change state to the opposite state if both S and R equal 1. Tables 7-1 a, b, and c below give the states for each type of flip flop for all states of input.
Inputs
S R
Output
Q
0 0
0 1
1 0
1 1
Latched
0
Invalid
1
S-R FF
Input
D
Output
Q
No equivalent
0
1
0
1
D-Latch
Inputs
J K
Output
Q
0 0
0 1
1 0
1 1
Latched
0
Toggle
1
J-K FF
No equivalent
Table 7-1a Table 7-1b Table 7-1c
The J-K FF will be used in this lab to demonstrate its unique capabilities.
Lab 7 – The JK FF 2
Procedure 1. Turn on computer and locate KeySight BenchVue software.
Turn on the Oscilloscope (reads outputs) / Function Generator (clock input). (You may need T.A. or instructor assistance) Construct the circuit of Figure 7-1 below. Set 𝑃𝑅𝐸̅̅ ̅̅ ̅̅ and 𝐶𝐿𝑅̅̅ ̅̅ ̅̅ to a logic 1. Connect the TTL signal from the function generator and set frequency to 1 Hz. Using the BenchVue software, save a screenshot of the input (Channel 1) and output, 𝑄, (Channel 2) for all combinations of J and K. Label all screenshots appropriately.
CLR
PRE
0V
330Ω
PRE
74LS76
CLK
J
CLR
Q
Q
K
330Ω
Red
+5V
1.0KΩ
c
J
K
Clock
indicator 0V
Pulse
generator
1 Hz
0V
330Ω
+5V
Green
Figure 7-1
2. Construct the circuit of Figure 7-2.
Using the BenchVue software save screenshots of the input (Channel 1) and output, �̅�, (Channel 2) for all combinations of J and K. Label all screenshots appropriately.
Figure 7-2
+5V
1.0KΩ
+5V
1.0KΩ
330Ω
PRE
74LS76
CLK
J
CLR
Q
Q
K
+5V
330Ω
Red
Green
Clock
indicator 0V
Pulse
generator
1 Hz
0V
330Ω
Yellow
Lab 7 – The JK FF 3
3. Construct the circuit of Figure 7-3. Using the BenchVue software save screenshots of the outputs, 𝑄1and 𝑄2 on the same screen (Channels 1 and 2) for all combinations of J and K. Then repeat this for outputs, �̅�1 and �̅�2 for all combinations of J and K. Label all screenshots appropriately.
+5V
Figure 7-3
330
PRE
74LS76
CLK
J
CLR
Q1
K
+5V
330Ω
Green
Clock
indicator 0V
Pulse
generator
1 Hz
0V
330Ω
Yellow
74LS76+5V
Red
1.0KΩ
+5V 1.0KΩ
Q1
PRE
CLK
J
CLR
K
Q2
Q2
Lab 7 – The JK FF 4
REQUIRED SUBMITTAL: You will NOT turn in this handout!!! You will do a formal lab report including the following sections: OBJECTIVE (Sentence format. Be thorough!) DATA –Use Multisim to create the circuits constructed in Figure 7-1, 7-2 and 7-3. Give each circuit a meaningful name that explains their function. Include labeled screenshots taken in the course of the lab (these should have labels similar to the circuit labels). DISCUSSION – (Sentence / Paragraph format) Discuss the operation and/or function performed by each of the (3) flip-flop circuits by analysis of the outputs.
