Digital Circuits & Systems i lab week 3
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ecet230_w3_lab_coversheet.docxLaboratory Report Cover Sheet DeVry University College of Engineering and Information Sciences
Course Number: ECET230
Professor:
Laboratory Number: 3
Laboratory Title: Flip-Flops in VHDL
Submittal Date: Click here to enter a date.
Objectives:
Results:
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Observations/Measurements:
IV. A. 2. D Flip-Flop Simulation:
PRE |
CLR |
D |
CLOCK |
Q |
Q_NOT |
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1 |
0 |
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0 |
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IV. B. 3 J-K Flip-Flop Simulation:
PRE |
CLR |
J |
K |
CLOCK |
Q |
Q_NOT |
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1 |
0 |
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0 |
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IV. C. . J-K Flip-Flop Propagation Delays:
tPHL = ______________________
tPLH = ________________________
Questions:
1.
3. Why were the LEDs removed before making the propagation delay measurements?
4. Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (PRE) is synchronous instead of asynchronous. The clear (CLR) remains asynchronous.
Grade:
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Deliverable |
Points Available |
Points Achieved |
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Laboratory Cover Sheet |
8 |
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Working Circuit(s)/Program(s) |
8 |
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Observations/Measurements |
6 |
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Questions |
8 |
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Total Points |
30 |
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Comments:
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Course Number: ECET-230 Laboratory Number: 4 Page 4 of 4
CLR
PRE
