Digital Circuits & Systems ilab week 2

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ecet230_w2_ilab_procedure_1.docx

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OBJECTIVES

1. To learn about the operation of a BCD-to-seven-segment decoder.

2. To learn about the operation of a seven-segment display.

3. To learn about the operation of multiplexers.

4. To build and test a circuit using a multiplexed display and eSOC III board.

5. To understand the use of bit and integer data types in VHDL.

6. To understand how to use integer addition or subtraction in a VHDL Dataflow architecture.

7. To compile and synthesize the VHDL file into files that can be used to program the eSOC II board.

8. To build a functioning 4-bit adder/subtractor in VHDL.

PARTS LIST

Equipment:

IBM PC or Compatible with Windows 2000 or Higher

Parts:

1 – eSOC III Board

Software:

MultiSim Version 11 or higher

Quartus II Design Software—Version 9.0

INTRODUCTION

The first part of this lab is to give practical experience in using decoders and multiplexers. The second part of this lab is the design of a 4-bit full adder using integer data types. This design involves inputting code, compiling, and simulating the design of an adder. The 4-bit adder circuit is expanded in the next part of the lab as a design project to create an adder/subtractor.

A seven-segment display is an array of seven bar-LEDs arranged to represent the decimal digits 0 to 9. To represent a digit, various segments (LEDs) are turned on and off. The layout of the seven-segment display used in this lab is shown in Figure 2.1. Note that on some chips, the pins with No Connect do not exist.

Any of the digits 0 => 9 can be displayed using the seven segments (actually a small eighth segment is there for a decimal point). To display a 0, we would turn off segment g and turn on all the others. To display a 1, b and c = on and the rest off and so on.

Figure 2.1: Common Anode Seven-Segment Display

This display is called a common anode type because the anodes (the positive sides, as opposed to the negative sides, which are call the cathodes) of the LEDs are connected together (pins 3, 9, 14) and tied to +5 volts. This means that a segment is turned on with a Logic 0 and turned off with a Logic 1. The common anode display is used more often than the common cathode because most logic devices can sink more current (Logic 0 output) than they can source (Logic 1 output).

PROCEDURE

A. Discrete Circuit Design

1. Using MultiSim, create the schematic for the circuit shown in Figure 2.2. The schematic must be drawn before building the circuit.

Figure 2.2: Multiplexer/Decoder Circuit (for Simulation)

2. Run various simulations to verify that the multiplexer is properly selecting the correct data inputs. Show results of an low and high data select to measurements and observations.

3. Online students, attach a copy of your circuit to the cover sheet.

B. Design Project

1. Develop the VHDL code to create the multiplexer-decoder circuit shown in Figure 2.2 for the eSOC III board, download the code, and submit the code and simulation to your instructor. Note that for the eSOC III board, the seven-segment display must be driven by active-HIGH signals as shown in Figure 2.4.

Figure 2.4: Multiplexer Circuit (eSOC Version)

To simplify the design, treat the circuit as a system rather than individual components.

As a system, the characteristics are as follows.

If A is LOW, then the output depends on the state of switches 0 to 3.

If 3,2,1,0 = “0000” then the output display = 0 = “1111110”

If 3,2,1,0 = “0001” then the output display = 1 = “0110000”

And so on.

If A is HIGH, then the output depends on the state of switches 4 to 7.

2. Photograph your final circuit for submission (online) or demonstrate your circuit to your professor (onsite or blended).

Instructor Sign Off ____________________ PROCEDURE

C. Design Entry and Simulation for 4-Bit Adder

1. Enter and compile the file for the 4-bit adder VHDL shown in Figure 2.5. Call this design add4bit.

ENTITY add4bit IS

PORT(

AI : IN INTEGER RANGE 0 to 15;

BI : IN INTEGER RANGE 0 to 15;

SOUT : OUT INTEGER RANGE 0 to 31);

END add4bit;

--Adds two four-bit inputs (AI and BI) to create a five-bit output sum (SOUT)

ARCHITECTURE adder4a OF add4bit IS

BEGIN

SOUT <= AI + BI;

END adder4a;

Figure 2.5: VHDL File for 4-Bit Integer Adder

2. Open the Waveform Editor, set the end time to 10.0S and grid to 500nS.

3. Use Node Finder to transfer AI, BI, and SOUT to the timing window.

4. Select AI (the whole bus) and click on the Count Value icon ( ). This function allows us to specify the operation of all of the signals in a bus. The window shown in Figure 2.6 will appear. Change the radix (the number system used) to Unsigned Decimal and press OK. A message will appear asking if you want to change the radixes of the other signals; press Yes.

Figure 2.6: Count Value Enable Window

5. With the settings shown in Figure 2.6, the AI bus will be increments from 0 to 15, and then begin the count again. The increment time is controlled by the Timing tab on the Count Value window.

6. In the Timing portion of the Count Value window, set the increment time to 500 nsec as shown in Figure 2.7. Click OK and the result should be as shown in Figure 2.8.

Figure 2.7: Count Value Increment Timing

Figure 2.8: Count Value Applied to Bus AI

7. Repeat Steps 5–7 for BI, except set the increment to 2.

8. Run the simulation and attach a hardcopy to your report.

D. Design Project: 4-Bit Adder and Subtractor

1. Design, simulate, and program a 4-bit adder/subtractor using VHDL and the eSOC III board to meet the following specifications.

a. Two 4-bit input buses—AI and BI.

b. One 5-bit output bus, SO.

c. A single select bit SEL to define the logic function. When SEL = 0, SO = AI + BI, and when SEL = 1, SO = AI – BI.

2. Develop the VHDL text file and verify the operation using circuit simulation. Create a program for the eSOC III board and download the program to the board.

3. Photograph your circuit for submission showing one addition and one subtraction (online) or demonstrate your circuit to your professor (onsite).

Instructor Sign Off __________________

4.Attach a copy of your VHDL program and simulation to your report.

Course Number: ECET-230 Laboratory Number: 2 Page 5 of 8

ABCDEFG

VCC

Key = 0

Key = 1

Key = 2

Key = 3

VCC

GND

74LS47N

~LT

~RBI

~BI/RBO

VCC

Key = 4

Key = 5

Key = 6

Key = 7

GND

74LS157N

~A/B

Key = S

Seven

Segment

Display

Pin 1 = Segment a

Pin 2 = Segment f

Pin 3 = Common Anode = +5V

Pin 9 = Common Anode = +5V

Pin 14= Comm

on Anode = +5V

Pin 4 = No Connect (NC)

Pin 5 = No Connect (NC)

Pin 12= No Connect (NC)

Pin 6 = Segment DP

Pin 7 = Segment e

Pin 8 = Segment d

Pin 10 = Segment c

Pin 11 = Segment g

Pin 13 = Segment b

Seven-Segment Display