programming assignment
lmoueomx
list_of_microcode_inst.docLIST OF MICROINSTRUCTIONS
|
INSTRUCTION |
MEANING |
|
0 |
Halt |
|
1 |
SDR <‑‑ ACC |
|
2 |
SDR <‑‑ PSIAR |
|
3 |
SDR <‑‑ TMPR |
|
4 |
ACC <‑‑ SDR |
|
5 |
PSIAR <‑‑ SDR |
|
6 |
TMPR <‑‑ SDR |
|
7 |
SAR <‑‑ ACC |
|
8 |
SAR <‑‑ PSAIR |
|
9 |
SAR <‑‑ TMPR |
|
10 |
ACC <‑‑ ACC + ACC |
|
11 |
ACC <‑‑ ACC + PSIAR |
|
12 |
ACC <‑‑ ACC + TMPR |
|
13 |
ACC <‑‑ ACC ‑ ACC |
|
14 |
ACC <‑‑ ACC – PSAIR |
|
15 |
ACC <‑‑ ACC ‑ TMPR |
|
16 |
ACC <‑‑ ACC |
|
17 |
ACC <‑‑ PSIAR |
|
18 |
ACC <‑‑ TMPR |
|
19 |
ACC <‑‑ ACC |
|
20 |
PSIAR <‑‑ ACC |
|
21 |
TMPR <‑‑ ACC |
|
22 |
ACC <‑‑ ACC + 1 |
|
23 |
ACC <‑‑ PSIAR + 1 |
|
24 |
ACC <‑‑ TMPR + 1 |
|
25 |
Read |
|
26 |
Write |
|
27 |
CSIAR <‑‑ CSIAR + 1 |
|
28 |
CSIAR <‑‑ decoded SDR |
|
29 |
CSIAR <‑‑ 0 |
|
30 |
SKIP (Add 1 to CSIAR if ACC = 0) |
|
31 |
DUMP |
|
32 |
MIR ( CSIAR |
MICROCODE DECODE TABLE
Machine Level
Mnemonic Op Code Control Storage Address
|
ADD |
1 |
10 |
|
SUB |
2 |
20 |
|
LOAD |
3 |
30 |
|
STORE |
4 |
40 |
|
BRANCH |
5 |
50 |
|
BRANCH ON 0 |
6 |
60 |
|
DUMP |
7 |
70 |
|
HALT |
8 |
80 |
|
BRANCH <> 0 |
9 |
90 |
