Code a Verilog module to implement the FSM

EEE 333: Hardware Design Languages (Verilog) and Programmable Logic

ASU, David R. Regenold, [email protected], GWC 348/349

L13 – Lab 3

A word on Debugging error messages (DRR’s opinion)

 Rarely (hardly ever) does one write code that is error- free on the first compile

 When you get a bunch of compile errors look at the first error first! – Seems intuitive, but since output scrolls, the last messages are

often the first you really see and many are tempted to start at the bottom.

– Many types of errors cascade into a snowball effect such that one issue leads to many others

 Understand what that first error is and fix it.  Browse through the others to see if any of them are

obviously similar.  Recompile and deal with the next wave of errors.

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Lab 3 - FPGA Design of Finite-State Machine

 Implement the following simple state machine on the BASYS-2 FPGA board. Any input transition not explicitly referenced in the diagram keeps the machine in the same state. Moreover, if two or more switches are asserted simultaneously, stay in the same state.

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Other requirements

 The clock for the FSM will be provided by you pressing PBC on the on the board. – Implement a debouncing circuit for this purpose (code

provided), otherwise you could get multiple clocks per button press.

 Display the machine states on the 4 digit, 7-segment displays as: – S_00  Use First 4 digits of your last name

– S_01  S_01

– S_02  S_02

– S_03  S_03

– S_04  S_04

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Why debounce?  Mechanical switches are

subject to bounce so that when you push one: – Instead of a nice transition like

this

– You get this (or worse)

 It appears that the BASYS-3 boards already have built in debounce protection.

 But I recommend using a debounce module just in case.

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A debounce module

 The onboard 100MHz clock

 The output of the pushbutton

 The “debounced”

version of the pushbutton output

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The 7-segment display Maybe the most challenging part of the lab

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 Each digit has a separate anode (controls are active low)

 But, there are 8 “common “

cathodes. (Also active low)

 Why? Pins are in high demand. We must attempt to achieve the functionality we desire with the fewest pins possible.

 Take advantage of the slow speed of human perception by only turning on a single digit at a time.

Mapping of cathodes to display segment

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Number examples using 7-segment display

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8’b00011111 8’b00000001 8’b00001001

Assumes an 8-bit quantity in this order

Timing Requirement for 7-segment display

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Note: The input clock is 100MHz (10ns cycle time). You must slow this down to from 1ms to 16ms. You’ll need to create the code to do this and to

properly mux the cathodes to match the desired digit.

Character set used for Lab 3 display

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Fast Review of something from Lecture 12 in response to a question.

State Diagram of an SRAM control

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st_read read=1 write=0

st_write read=0 write=1

st_delay read=0 write=0

reset

slow_ram = 1’b1

slow_ram = 1’b0

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Verilog for SRAM Control

FSM code is generally divided into two separate processes: one for the sequential behavior and one for the combinational logic

What if coded like this

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Combined the case statement under the clock activated always loop.

Simulations

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Bottom four signals are from modified code. Note the change in behavior.

Summary

 In effect, the speed of the resultant circuit is now half the speed of the clock.

 When implemented in hardware (a topic of a future lecture), many more flip-flops will be used because the “next-state” will now require Flip-flops.

 Conclusion  – Keep “current-state” behavior in an always block with the

clock in the sensitivity list (flip-flop implementation)

– Keep “next-state” behavior in an always block with the “current-state” and inputs in the sensitivity list (combinational logic).

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