basic logic gate homework

X Y Z ZYX  ZYX  X Y Z ZYX  0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

EEE 333, ASU

David R. Regenold

Homework #1 – Due Tuesday, Jan 26

The objective of this homework is to practice your knowledge of combinational and sequential

logic, as well as the implementation with CMOS gates.

1. Boolean Logic

DeMorgan’s Law for three variables: ZYXZYX  Prove the theorem by constructing a truth table for each term:

2. Transistor Level Gates

Consider a one stage static CMOS gate which implements the following function.

geff 

a) How many transistors are required?

b) Draw the transistor-level schematic of the gate.

3. CMOS Implementation

Given primary inputs A and B, and using 2-input NAND gates only, simplify the following

expressions and construct the logic path with the minimum number of gates.

(a)   fffe  (b) )( trtr  (c) ))(( BAAB  (d) BABA 

4. Sequential Logic

a) Consider the above sequential circuit. Assume that at time zero, All Q’s are 0 (and, of

course, all Q_bar’s are 1). Fill out the following table giving the values of Q2, Q1, and

Q0 after each rising edge of the CLK.

Time Q2 Q1 Q0

Initial Value 0 0 0

After CLK Rising Edge 1

After CLK Rising Edge 2

After CLK Rising Edge 3

After CLK Rising Edge 4

After CLK Rising Edge 5

After CLK Rising Edge 6

After CLK Rising Edge 7

After CLK Rising Edge 8

b) Describe what this counter is doing.

I.E., how does it differ from an ordinary up counter?