Computer Systems Architecture Assignment/Lab/Discussion/Project
beoto01
it321_m6_memory_hierarchy.zipIT321_M6D.docx
1. Memory refers to the physical devices used to store programs or data. Main memory is used for the information in physical systems which function at high speed (i.e. RAM), as compared to secondary memory, which are physical devices for program and data storage which are slow to access but offer higher memory capacity.
The cache memory is an intermediate level between the main memory and the processor. The goal is to store the most frequently and most recently accessed data in the upper-level unit (cache) to make returning to it much faster. Can this concept be used in any real life applications? If so, discuss its use and advantages.
2. Virtual memory is an old concept; before computers had caches, they had virtual memory. For a long time, virtual memory only appeared on mainframes. Personal computers in the 1980s did not use virtual memory. In fact, many good ideas that were in common use in the UNIX operating systems didn't appear in personal computer operating systems until the mid-1990s.
Discuss the advantages of virtual memory. Identify some real-life applications of virtual memory and discuss why virtual memory would be beneficial in those situations.
M6A1 Assignment Memory.docx
A memory cache, sometimes called a cache store or RAM cache, is a portion of memory made of high-speed static RAM (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory. Memory caching is effective because most programs access the same data or instructions over and over. By keeping as much of this information as possible in SRAM, the computer avoids accessing the slower DRAM.
Compose your responses to the following questions in one document and make your submission to the drop box before the end of this module.
1. Consider two alternate caches, each with four sectors holding one block per sector and one 32-bit word per block. One cache is direct mapped, and the other is fully associative with least recently used (LRU) replacement policy. The machine is byte addressed on word boundaries and uses write allocation with write back.
What would the overall miss ratio be for the following address stream on the direct mapped cache? Assume the cache starts out completely invalidated.
read 0x00
read 0x04
write 0x08
read 0x10
read 0x08
write 0x00
You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes.
The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32KB each, with a block size of 64 bytes.
◦The I-cache has a 2% miss rate, and the D-cache is a write-through with 5% miss rate. .
◦The hit cycles for both the I-cache and the D-cache take 1 cycle (1 cycle takes 1 ns). .
◦The L2 cache is a unified write-back with a total size of 512 KB and a block size of 64 bytes. .
◦The hit cycle of the L2 cache is 15 cycles. The local hit rate of the L2 cache is 80%. .
◦An L2 data write miss takes extra 15 ns.
Given: Hit time=Hit Rate*Hit Cycles
L2 miss penalty = 100nsec
Compute the AMAT for both instruction and data memories.
M6A2_Lab Procedures.docx
Lab 4 –MIPS Assembly language
Programming with MARS IDE Procedures
The purpose of this lab is to introduce you to the layout and structure of the Mars IDE development tool in addition to Procedures programming. In this lab, a procedure is called to sort three numbers (ascending sort) in the memory.
Procedure:
I. Follow the same procedure in Lab1.
II. From the main menu, choose “File” “New”
III. You will find a blank file. Start typing your program. The main program and the procedure
Type the program provided below in the screen shot.
IV. Click on the icon “Assemble the current file”
V. Run the given program
· Observe the registers/Memory locations values after each Step Run. Record the final values.
· Use $t0, $t1, and $t2 to hold the numbers after the ascending sort. What are the final values of $t0, $t1, and $t2?
Things to turn in as your Lab 4 Report, attached in this order:
1- Your name, Course Number, Lab Number and Date
2- Screen shot of the Program
3- Results/Observations such as the final screen shot of the registers and memory locations
4- Questions with answers
6- References if any
image1.png
M6A3 Assignment Project Milestone 3 Memory Characteristics.docx
In this activity, you will work as a student to identify the memory structure for your proposed architecture. You should define its size, unique parameters, and the instructions that deal with the memory. You need to determine the cache levels and how cache works in your proposed structure.
In this module, each student will submit the proposed processor architecture. In your proposed architecture, specify the following:
1. Determine the memory structure used in your computer architecture.
◦You may choose to have a unified memory for both data and instructions or you may prefer a separate memory for each.
2. Determine the size of your proposed memory.
3. Determine what instructions can access the memory and how.
◦In the previous milestone, you determined all the instructions that can be handled in the proposed computer architecture. In this milestone, determine what instructions can access the memory and how.
4. Determine the cache levels.
◦You may choose to have one or more cache levels. In each cache level, you have to determine if this level is a unified or a separate cache for both data and instructions. In addition, you have to select the cache size for each level.
5. Determine how cache works.
◦Determine how to locate a block in the cache, and how to choose a block to be replaced from the cache.
Project Milestone 2 Processor Components.pdf
Will work as a student to identify a set of processor parameters and structures. You need to define the components, unique parameters, and instruction set for your proposed processor structure. To determine the instruction set, you will have to create your own set of instructions that your processor can handle.
Each student will submit their proposed processor architecture. In your proposed architecture, specify the following:
Processor architecture and instruction set:
1. Determine the processor components and the characteristics for each component.
• Components may be any internal hardware that your proposed processor may have, such as a special arithmetic unit.
2. Determine how many registers there are in your computer architecture.
• You have to specify how many registers are in your proposed processor, their names, and their sizes. You may have three registers A, B, and C. Each register is 8 bits. You do not have to stick with the MIPS structure given in the course.
3. Determine the instructions that your proposed processor can handle.
• You have the freedom to determine how many instructions your proposed processor can handle. You have to have more than ten instructions. Your instructions can be anything, including instructions such as add, sub, and mul.
4. Determine the instruction size.
• Determine the size of your proposed instruction set. You may choose to have a varying or fixed instruction set size. Discuss why you selected that type of instruction set.
Instruction type and format:
1. Determine how many instruction types your processor will support.
• The instruction types can be R-type for arithmetic, J-type for jump, or any other types you would like. You may have one type or more. Determine the format of each type. For each instruction type, determine the size and the format. You may use the same format for all types, or different formats for each. For each format, determine how many fields it has, and the size of each field. For example, you may have three fields with each field being six bits. That will give you an eighteen bit instruction. The first field may be the op-code, the second field may be the source register, and the third field may be the destination register.
2. Determine the format of each type.
• For each instruction type, determine the size and the format. You may use the same format for all types, or different formats for each. For each format, determine how many fields it has, and the size of each field. For example, you may have three fields with each field being six bits. That will give you an eighteen bit instruction. The first field may be the op-code, the second field may be the source register, and the third field may be the destination register.
