Digital Electronics MultiSim Lab

ELEC201 Digital Electronics

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Excelsior College

Module 6: Laboratory 1: Design of Synchronous Sequential Counter

Problem Statement:

Design an up/down counter with four states (0, 1, 2, 3) using clocked J-K flip-flops. A control signal x is used as follows: When x = 0 the machine counts forward (up), when x = 1, backward (down). Simulate using MultiSim and attach a simulation printout.

Please address the following in your report:

1. State Table 2. State Diagram 3. Flip-Flop Excitation Tables 4. K-Map Simplification and resulting diagram 5. Multisim Simulation 6. Conclusion/Discussion 7. References