ECE320 digital design " Sequential circuits " HW

ECE 2320 – Homework No.7 R. Roosta

1. Circuit below is a two’s complement generator using J K flip flops. When control is 1 this circuit generates the two’s complement of these 7 flip flops. Delay of each flip flop from time that CP goes from 0 to 1 and its output will be completed is 10 ns and delay for each and gate is 5 ns and for or gates is 2 ns. What is the maximum delay and maximum frequency of this circuit?

Q6 J K Q5 J K Q4 J K Q3 J K Q2 J K Q1 J K Q0 J K control clock

2. Use 8 x 4 memory blocks and construct a 32 x 8 memory.

3. Draw a diagram for a 8 x 4 memory block.

4. Design a BCD to 7 4-2-1 code converter using a ROM

5. Solve problem 4 using PLA.

6. Minimize the following state diagram (it contains redundant states) find them and then redraw a minimized state diagram. Show your work.

A B D C E F 0/0 1/0 1/0 0/0 0/0 0/0 0/1 1/0 1/0 0/1 1/0 1/0

7. Use a universal counter that counts up, down, and has the ability of clear and load based on table below, and extra needed components and gates. Design a module-9 counter that counts sequence (0,1,2,3,4,11,12,13,14) when it counts up and counts in the reverse sequence (14,13,12, 11, 4, 3,2, 1,0) when it counts down

Universal counter functional table

clear	load	Up/down	clock	counter
1	x	x		0
0	1	x		Data_in
0	0	1		Counter + 1
0	0	0		Counter - 1

8. Design an Up/down counter with the ability of loading and clear using T flip flop based on table below.

load	Up/down	clock	Counter
x	x		0
1	x		Data_in
0	1		Counter + 1
0	0		Counter – 1

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