Electrical Engineering Digital Logic Design

1. Designing a 2-bit binary Comparator.

You are asked to design a 2-bit comparator. The inputs to the comparator are two 2-bit binary numbers X and Y. X is composed of bits x1 and x0 and Y is composed of bits y1 and y0. Bit subscripts corresponds to the significance i.e. x1 is the MSB of X and x0 is the LSB of X and the same goes for Y. The circuit takes these 4 input bits and outputs three outputs EQ (i.e. X=Y), YGX (i.e. Y > X), and XGY (i.e. X > Y).

Answer the Following questions and do as instructed in the sub- parts that follow. If you use truth tables then make the bits of Y the MSB and the bits of X the LSB as follows: y1 y0 x1 x0

. a) Derive an expression for the EQ output that is minimum in the number of literals not necessarily SOP or POS. Hint: You don’t have to use a truth table for this as long as you explain how you arrived to the expression. ���

. b) Derive an expression for YGX that is minimal in the number of literals [You can get this through an initial SOP expression]. You have to show your work for the expression. ���

. c) Derive an expression for XGY using EQ and YGX only. ���

2. You are developing a monitoring system for an automobile to be used for new drivers. The system will be able to log a warning message if the vehicle exceeds a certain speed or if the vehicle is being operated outside of allowed hours whether it is driven or not. You should assume that the following variables are recorded once the vehicle is turned on:

. Whether the car is in reverse? (R)

. Whether the car is in drive? (D)

. Whether the car is turned on (not necessarily moving though) outside of the allowed hours for new drivers, and (H)

. Whether the pre-set speed limit has been exceeded if the car is moving. (S)

You may assume that if the car is not in reverse or in drive that it is not in gear i.e. it is not moving. You may also assume that exceeding the speed limits for forward and reverse are recorded using the same variable i.e. there is a limit for reverse too. Order the variables in a truth table should you need one as: R D H S

Use the variable names as indicated above next to each recorded event to come up with an expression representing the warning function W. Hint: A truth table might help but is not necessary if you can reason about the expression for W.

3. Recall that a full adder (FA) is a circuit that adds two bits and a carry in to produce a sum bit and a carry out. Assume the inputs to the FA are X, Y (the two bits) and C (the carry in). Maintain this order for truth tables X is the leftmost variable and C is the rightmost variable. The outputs of the FA are labeled S (Sum) and Cout (Carry out). Note that S is the LSB and Cout is the MSB.

Implement both S and Cout using only one decoder with active-low outputs. Clearly mark its inputs, outputs, and its size. Use only a minimum number of gates with minimum fan-in if should you need any gates.

4. Implement the following Boolean function using a 4x1 multiplexer. Use only a minimum number of gates with minimum fan-in if should you need any gates. Use inputs C, D for the select inputs of the multiplexer (S1, S0) respectively.

F (A, B, C, D) = 𝜋M(1,  3,4,6,9,11), with the following don’t care conditions: d(A, B, C, D)=∑  𝑚(0,2,5,10,12,14)  

5. Design a two-bit comparator from two 1-bit comparators as the building blocks. Note: Problem 1 can help in solving this one.

Assume you have access to two of these 1-bit comparators that we have built in lecture. Namely, comparators C0 and C1. You are given two 2-bit binary numbers X and Y. X is composed of bits x1 and x0 and Y is composed of bits y1 and y0. Bit subscripts corresponds to the significance i.e. x1 is the MSB of X and x0 is the LSB of X and the same goes for Y. Each Comparator outputs are labeled as follows:

EQ0 (i.e. y0 = x0), YGX0 (i.e. y0 > x0), and XGY0 (i.e. y0 < x0) for Comparator C0. EQ1 (i.e. y1 = x1), YGX1 (i.e. y1 > x1), and XGY1 (i.e. y1 < x1) for Comparator C1. The Comparator to be designed is called “C”. The outputs of that Comparator are:

EQ (i.e. Y = X), YGX (i.e. Y > X), and XGY (i.e. Y < X).

Your task is to derive an expression for the three outputs of the 2- bit comparator that you are designing. Namely, Express EQ, XGY, YGX as functions of EQ0, YGX0, XGY0, EQ1, YGX1, and XGY1 and not as functions of x0, y0, x1, nor y1.