Assembly HW

ELEC 385: Computer System Design Homework #13

Due: April 24, 2015 1. Consider the following code. Trace the execution of the following code through the

pipelined processor using as many copies of the attached pipelining template as needed. Clearly indicate the relevant inputs, outputs and control signals for each stage of the pipeline during each clock cycle. Assume the initial state of the processor as shown. You should have one picture of the pipeline for each clock cycle required to completely execute the code. t0 = 0xF780FFE7 t1 = 0x00205800 t2 = 0x1E80FF00 t3 = 0x9DF7AB33 t4 = 0xEF76F790 t5 = 0x41CCE15D

.eqv Result,-2

.text add $t0,$t1,$t2 ori $t5,$t4,0xF00D sw $t3,Result($t2)

2. Determine the execution time for the code to run on each of the microarchitectures listed below. Show all work. For the pipelined microarchitectures it may be helpful to first identify any hazard that cannot or will not be resolved and then insert nops in the code, rather than try to trace through a pipeline. That way you don’t have to count clock cycles and check for hazards at the same time. Also, for ease of comparison assume the structure in Figure 7.58 for both pipelining microarchitectures. a) Single-cycle microarchitecture b) Multicycle microarchitecture c) Pipeline microarchitecture with hazard detection, but no data forwarding. d) Pipeline microarchitecture with hazard detection and data forwarding

addi $t0,$0,5 add $t2,$0,$0 here: lw $t3,($t1) add $t2,$t2,$t3 addi $t1,$t1,4 addi $t0,$t0,-1 bne $t0,$0,here sw $t2,4($t1)

Show all work. And, as always, homework is to be single-sided and stapled.