ModelSim for VHDL

Lab Assignment #5 FINITE STATE MACHINE – SEQUENCE DETECTOR

Description The objective for this lab is to use the previous knowledge obtained with VHDL behavioral design to design and implement a Moore finite state machine that will detect a sequence of input bits. Also use the knowledge obtained about VHDL test-benches to create a test bench to test the design and implementation of the sequence detector. Work-To-Do The sequence detector will detect the input sequence of ‘1001’ and will output ‘1’ whenever that sequence is detected otherwise will output ‘0’. The sequence detector must be implemented with a Moore finite state machine design, which the output of the machine is only dependent on the current state the machine is in. The following specifications for the design must be met:

1. The input and output are single bits. 2. The clock should have a 20ns period and be high/low for the same amount of time. 3. The finite state machine must have a reset option that will reset the output to ‘0’ and set the

state to the initial/beginning state. 4. The state machine should update the state whenever a rising edge of a clock occurs.

a. So there must be a clock in the design. b. This also means that whatever the input is at the time of the clock (regardless if it

changed) will be considered the new input. The test-bench can provide any input but must AT LEAST test getting the ‘1001’ input combination to test the state machine. The timing for the test bench should take into consideration the clock to be able to get the expected correct results. Expected Results

1. Turn in the Moore finite state machine diagram used for the design for the lab. 2. Simulations for the sequence detector showing the correct behavior. 3. Code for both the finite state machine and test-bench being used to test the machine.