EECE144 logic design

Here is the 2x1 Mux: module      Mux_2_1(I0, I1, s, out);

input         I0, I1, s;

output      out;

wire        s_not, T1, T2;

not (s_not, s);

and(T1, I0, s_not);

and(T2,  I1, s);

or(out, T1, T2);

endmodule

/*module       test(  );

reg                        I0, I1, s;

wire            out;

Mux2_1      muxtest1(I0, I1, s);

initial      

begin

I0=0;    I1=0;   s=0;

#10   I0=1;

#10   I1=1;

#10   s=1;

#10   I0=1;

#10   I1=0;

#10   s=1;

#10   I0=1;

#10   I1=1;

#10   s=0;

#10   I0=0;

#10   I1=1;

#10   s=1;

end

endmodule*/

Here is the 8x1 Mux: module        Mux8_1(n0, n1, n2, n3, n4, n5, n6, n7, x, y, z, out);

                      

input         n0, n1, n2, n3, n4, n5, n6, n7, x, y, z;

output     out;

wire         w1, w2, w3, w4, w5, w6;

Mux2_1     mux1(n0, n1, z, w1);

Mux2_1     mux2(n2, n3, z, w2);

Mux2_1     mux3(n4, n5, z, w3);

Mux2_1     mux4(n6, n7, z, w4);

Mux2_1     mux5(w1, w2, y, w5);

Mux2_1     mux6(w3, w4, y, w6);

Mux2_1     mux7(w5, w6, x, out);

endmodule

module       mux8to1test();

reg      n0, n1, n2, n3, n4, n5, n6, n7, x, y, z;

wire   o;

Mux8_1    muxtest2(n0, n1, n2, n3, n4, n5, n6, n7, x, y, z, o);

initial      

begin

n0=0;   n1=0;    n2=0;    n3=0;   n4=0;     n5=0;      n6=0;      n7=0;      x=0;     y=0;     z=0;

#10    n0=1;

#10    n1=1;

#10    n2=1;

#10    n3=1;

#10    n4=1;

#10    n5=1;

#10    n6=1;

#10    n7=1;

#10    x=1;

#10    y=1;

#10    z=1;

#10    n0=1;

#10    n1=0;

#10    n2=1;

#10    n3=0;

#10    n4=1;

#10    n5=0;

#10    n6=1;

#10    n7=0;

#10    x=1;

#10    y=0;

#10    z=1;

#10    n0=1;

#10    n1=0;

#10    n2=0;

#10    n3=1;

#10    n4=0;

#10    n5=0;

#10    n6=1;

#10    n7=0;

#10    x=0;

#10    y=1;

#10    z=0;

end

endmodule

Here is the 5 bit adder:          module  five_bits(a,b,cin,s,cout4, V);

input   [4:0]a,b;

input   cin;

output  [4:0]s;

output  cout4, V;

wire    [4:0] bcom;

wire    cout0,cout1,cout2,cout3;

assign  bcom[0]=b[0]^cin;

assign  bcom[1]=b[1]^cin;

assign  bcom[2]=b[2]^cin;

assign  bcom[3]=b[3]^cin;

assign  bcom[4]=b[4]^cin; FA         FA0(a[0],bcom[0],cin,s[0],cout0),

          FA1(a[1],bcom[1],cout0,s[1],cout1),

          FA2(a[2],bcom[2],cout1,s[2],cout2),

          FA3(a[3],bcom[3],cout2,s[3],cout3),

          FA4(a[4],bcom[4],cout3,s[4],cout4);

assign V= cout3^cout4;

endmodule

module test;

reg [4:0] a, b;

reg carryin;

wire [4:0]result;

wire carryout, overflow;

initial

begin

a=0; b=0; carryin=0;

#10 a=0; b=0; carryin=1;

#10 a=1; b=4; carryin=0;

#10 a=20; b=8; carryin=1;

#10 a=17; b=3; carryin=1;

#10 a=3; b=11; carryin=1;

#10 a=26; b=18; carryin=0;

#10 a=5; b=7; carryin=1;

end

five_bits add_sub(a, b, carryin, result, carryout, overflow);

initial

$monitor("at time %t, A=%d B=%d cin=%b result=%d(%b) cout=%b overflow=%b",

         $time, a, b, carryin, result, result, carryout, overflow);

endmodule

Here is the first fall adder:         module  FA(A,B,CIN,S,COUT);

input   A,B,CIN;

output  S,COUT;

assign  S = A^B^CIN;

assign  COUT= (A && B) | (A && CIN) | (B && CIN);

endmodule